4559 Datasheet, PDF (27/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
EXTERNAL INTERRUPTS
The 4559 Group has the external 0 interrupt. An external
interrupt request occurs when a valid waveform is input to an
interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.
Table 14 External interrupt activated conditions
Name
Input pin
Activated condition
External 0 interrupt D5/INT
When the next waveform is input to D5/INT pin
• Falling waveform (“H” → “L”)
• Rising waveform (“L” → “H”)
• Both rising and falling waveforms
Valid waveform
selection bit
I11
I12
(Note 1)
D5/INT
(Note 1)
I13
I12
Falling
0
1
Rising
K20
One-sided edge
I11
detection circuit
0
or
1
Both edges
detection circuit
SNZI0 instruction
EXF0
External 0
interrupt
Timer 1 count start
synchronization
circuit input
Skip
(Note 2) _K21
Level detection circuit
0
Edge detection circuit
1
Key-on wakeup input
(Note 3)
Note 1:
This symbol represents a parasitic diode on the port.
2: When I12= 0(X=0 or 1) is 0, “L” level is detected.
When I12 is 1, “H” level is detected.
3: When I12 is 0, falling edge is detected.
When I12 is 1, rising edge is detected.
Fig 28. External interrupt circuit structure
Rev.1.04 Aug 23, 2007 Page 27 of 146
REJ03B0188-0104