4559 Datasheet, PDF (36/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
When bit 1 of register W4 is set to “1”, the PWM signal output to
CNTR pin is switched to valid/invalid each timer 1 underflow.
However, when timer 1 is stopped (bit 2 of register W1 is cleared
to “0”), this function is canceled.
Even when bit 1 of a register W2 is cleared to “0” in the “H”
interval of PWM signal, timer 2 does not stop until it next timer 2
underflow.
When clearing bit 1 of register W2 to “0” to stop timer 2, avoid a
timing when timer 2 underflows.
(8) Timer interrupt request flags (T1F, T2F, T3F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the
skip instructions (SNZT1, SNZT2, SNZT3).
Use the interrupt control register V1, V2 to select an interrupt or
a skip instruction.
An interrupt request flag is cleared to “0” when an interrupt
occurs or when the next instruction is skipped with a skip
instruction.
(5) Timer 3 (interrupt function)
Timer 3 is a 16-bit binary down counter.
Timer 3 starts counting after the following process;
(1) set count value by bits 0 and 1 of register W3,
(2) set count source by bit 3 of register W3, and
(3) set the bit 2 of register W3 to “1.”
Once count is started, when timer 3 underflows (the set count
value is counted), the timer 3 interrupt request flag (T3F) is set to
“1,” and count continues.
Bit 4 of timer 3 can be used as the timer LC count source for the
LCD clock generating.
When bit 2 of register W3 is cleared to “0”, timer 3 is initialized
to “FFFF16” and count is stopped.
Timer 3 can be used as the counter for clock because it can be
operated at clock operating mode (POF instruction execution).
When timer 3 underflow occurs at clock operating mode, system
returns from the power down state.
When operating timer 3 during clock operating mode, set 1 cycle
or more of count source to the following period; from setting bit
2 of register W3 to “1” till executing the POF instruction.
(6) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC
reload register (RLC). Data can be set simultaneously in timer
LC and the reload register (RLC) with the TLCA instruction.
Data cannot be read from timer LC. Stop counting and then
execute the TLCA instruction to set timer LC data.
Timer LC starts counting after the following process;
(1) set data in timer LC,
(2) select the count source with the bit 2 of register W4, and
(3) set the bit 3 of register W4 to “1.”
(9) Count start synchronization circuit (timer 1)
Timer 1 has the count start synchronous circuit which
synchronizes the input of INT pin, and can start the timer count
operation.
Timer 1 count start synchronous circuit function is selected by
setting the bit 0 of register I1 to “1” and the control by INT pin
input can be performed.
When timer 1 count start synchronous circuit is used, the count
start synchronous circuit is set, the count source is input to timer
by inputting valid waveform to INT pin.
The valid waveform of INT pin to set the count start synchronous
circuit is the same as the external interrupt activated condition.
Once set, the count start synchronous circuit is cleared by
clearing the bit I10 to “0” or system reset.
However, when the count auto-stop circuit is selected, the count
start synchronous circuit is cleared (auto-stop) at the timer 1
underflow.
(10)Count auto-stop circuit (timer 1)
Timer 1 has the count auto-stop circuit which is used to stop
timer 1 automatically by the timer 1 underflow when the count
start synchronous circuit is used.
The count auto-stop circuit is valid by setting the bit 3 of register
W1 to “1”. It is cleared by the timer 1 underflow and the count
source to timer 1 is stopped.
This function is valid only when the timer 1 count start
synchronous circuit is selected.
When a value set in reload register RLC is n, timer LC divides
the count source signal by n + 1 (n = 0 to 15).
Once count is started, when timer LC underflows (the next count
pulse is input after the contents of timer LC becomes “0”), new
data is loaded from reload register RLC, and count continues
(auto-reload function).
Timer LC underflow signal divided by 2 can be used for the LCD
clock.
(7) Timer input/output pin (C/CNTR pin)
CNTR pin is used to input the timer 1 count source and output
the PWM signal generated by timer 2. The selection of CNTR
output signal can be controlled by bit 3 of register W2.
When the PWM signal is output from C/CNTR pin, set “0” to the
output latch of port C.
When the CNTR input is selected for timer 1 count source, timer
1 counts the waveform of CNTR input selected by bit 0 of
register W4. Also, when the CNTR input is selected, the output
of port C is invalid (high-impedance state).
Rev.1.04 Aug 23, 2007 Page 36 of 146
REJ03B0188-0104