4559 Datasheet, PDF (45/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
(4) LCD drive waveform
When “1” is written to a bit in the LCD RAM data, the voltage
difference between common pin and segment pin which
correspond to the bit automatically becomes lVLC3l and the
display pixel at the cross section turns on.
When returning from reset, and in the RAM back-up mode, a
display pixel turns off because every segment output pin and
common output pin becomes VLC3 level.
1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 8) in RAM.
M (1, 2, 8)
COM0 _{0 (bit 0)}
COM1 ₁
COM1
1 flame (2/F)
1/F
X
X (bit 3)
SEG16
COM0
SEG16
COM1
SEG16
ON
COM0
SEG16
OFF
1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 8) in RAM.
M (1, 2, 8)
COM0 _{1 (bit 0)}
COM1 ₀
COM2 ₁
X (bit 3)
COM2
COM1
1 flame (3/F)
1/F
SEG16
COM0
SEG16
COM2
SEG16
ON
COM1
SEG16
OFF
COM0
SEG16
ON
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 8) in RAM.
M (1, 2, 8)
COM0 _{0 (bit 0)}
COM1 ₁
COM2 ₀
COM3 _{1 (bit 3)}
COM3
COM2
1 flame (4/F)
1/F
SEG16
COM1
COM0
F : LCD clock frequency
SEG16
X: Set an arbitrary value.
(These bits are not related to
set the drive waveform at each duty.)
Fig 46. LCD controller/driver structure
COM3
SEG16
ON
COM2
SEG16
OFF
COM1
SEG16
ON
COM0
SEG16
OFF
Rev.1.04 Aug 23, 2007 Page 45 of 146
REJ03B0188-0104
Voltage level
VLC3
VLC1=VLC2
VSS
VLC3
VLC1=VLC2
VSS
Voltage level
VLC3
VLC2
VLC1
VSS
VLC3
VLC2
VLC1
VSS
Voltage level
VLC3
VLC2
VLC1
VSS
VLC3
VLC2
VLC1
VSS