4559 Datasheet, PDF (64/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
(7) Clock control register MR
Register MR controls system clock and operation mode
(frequency division of system clock). Set the contents of this
register through register A with the TMRA instruction. In
addition, the TAMR instruction can be used to transfer the
contents of register MR to register A.
(8) Clock control register RG
Register RG controls the start/stop of each oscillation circuit. Set
the contents of this register through register A with the TRGA
instruction.
Table 28 Clock control registers
Clock control register MR
MR3
Operation mode selection bits
MR2
MR1
System clock selection bits (Note 2)
MR0
at reset : 11002
at power down : state retained
MR3 MR2
Operation mode
0 0 Through mode
0 1 Frequency divided by 2 mode
1 0 Frequency divided by 4 mode
1 1 Frequency divided by 8 mode
MR1 MR0
System clock
0 0 f(RING)
0 1 f(XIN)
1 0 f(XCIN)
1 1 Not available (Note 3)
R/W
TAMR/TMRA
Clock control register RG
at reset : 0002
at power down : state retained
W
TRGA
RG2 Sub-clock (f(XCIN)) control bit (Note 4)
0
Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected
1
Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected
RG1 Main-clock (f(XIN)) control bit (Note 4)
0
Main clock (f(XIN)) oscillation available
1
Main clock (f(XIN)) oscillation stop
RG0
On-chip oscillator (f(RING)) control bit
(Note 4)
0
On-chip oscillator (f(RING)) oscillation available
1
On-chip oscillator (f(RING)) oscillation stop
Note 1. R” represents read enabled, and “W” represents write enabled.
Note 2. The stopped clock cannot be selected for system clock.
Note 3. “11” cannot be set to the low-order 2 bits (MR1, MR0) of register MR.
Note 4. The oscillation circuit selected for system clock cannot be stopped.
Rev.1.04 Aug 23, 2007 Page 64 of 146
REJ03B0188-0104