4559 Datasheet, PDF (50/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4559 Group
(2) Power-on reset
Reset can be automatically performed at power on (power-on
reset) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, set the time for the supply voltage
to rise from 0 V to the minimum voltage of recommended
operating conditions to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between
the RESET pin and Vss at the shortest distance, and input “L”
level to RESET pin until the value of supply voltage reaches the
minimum operating voltage.
(3) System reset instruction (SRST)
By executing the SRST instruction, “L” level is output to RESET
pin and system reset is performed.
100µs or less
VDD (Note)
Power-on reset
circuit output
Internal reset signal
Power-on Reset Reset
state released
Note: Keep the value of supply voltage to
the minimum value or more of the
recommended operating conditions.
Fig 50. Power-on reset operation
Table 21 Port state at reset
Name
Function
D0−D4
D0−D4
D5/INT
D5
XCIN/D6, XCOUT/D7
XCIN, XCOUT
P00/SEG16−P03/SEG19
P00−P03
P10/SEG20−P13/SEG23
P10−P13
P20/SEG24−P23/SEG27
P20−P23
P30/SEG28−P33/SEG31
P30−P33
SEG0/VLC3−SEG2/VLC1
SEG0−SEG2
SEG3−SEG15
SEG3−SEG15
COM0−COM3
COM0−COM3
C/CNTR
C/CNTR
Note 1. Output latch is set to “1.”
Note 2. The output structure is N-channel open-drain.
Note 3. Pull-up transistor is turned OFF.
State
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
Sub-clock input
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
VLC3 (VDD) level
VLC3 (VDD) level
VLC3 (VDD) level
“L” (VSS) level
Rev.1.04 Aug 23, 2007 Page 50 of 146
REJ03B0188-0104