HYB18T256161BF Datasheet, PDF(8/40 Page) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

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HYB18T256161BF Datasheet, PDF (8/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

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Internet Data Sheet

HYB18T256161BFâ20/25/28

256-Mbit Double-Data-Rate-Two SDRAM

Abbreviation

SSTL

LV-CMOS

CMOS

OD

TABLE 4

Abbreviations for Buffer Type

Description

Serial Stub Terminated Logic (SSTL_18)

Low Voltage CMOS

CMOS Levels

Open Drain. The corresponding ball has 2 operational states, active low and tristate, and

allows multiple devices to share as a wire-OR.

FIGURE 1

Chip Configuration, PG-TFBGA-84 (top view)

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Notes

1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is

data strobe for DQ[7:0]

2. LDM is the data mask signal for DQ[7:0], UDM is the data

mask signal for DQ[15:8]

3. VDDL and VSSDL are power and ground for the DLL. VDDL is

connected to VDD on the device. VDD, VDDQ, VSSDL, VSS,

and VSSQ are isolated on the device.

Rev. 1.20, 2007-06

8

11232006-QP6X-6EM0

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