HYB18T256161BF Datasheet, PDF (27/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

Internet Data Sheet
5.7
AC Characteristics
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
5.7.1
Speed Grade Definitions
TABLE 28
Speed Grade Definition
Speed Grade
Symbol –20
–25
–28
Unit Note
Parameter
Min. Max. Min. Max. Min. Max.
Clock
Frequency
@ CL = 3 t_CK
@ CL = 4 t_CK
5
8
3.75 8
5
8
3.75 8
5
8
3.75 8
ns
1)2)3)4)
ns
1)2)3)4)
@ CL = 5 t_CK
3
8
3
8
3
8
ns
1)2)3)4)
@ CL = 6 t_CK
2.5
8
2.5
8
2.8
8
ns
1)2)3)4)
@ CL = 7 t_CK
2.0
8
—
—
—
—
ns
1)2)3)4)
Row Active Time
t_RAS
45
70k
45
70k
45
70k
ns
1)2)3)4)5)
Row Cycle Time
t_RC
60
—
60
—
60
—
ns
1)2)3)4)
RAS-CAS-Delay
t_RCD
15
—
15
—
15
—
ns
1)2)3)4)
Row Precharge Time
t_RP
15
—
15
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8Timings
are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements” according
to Chapter 7.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, input reference
level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS is defined in
Chapter 7.3.
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
4) The output timing reference voltage level is V_TT. See Chapter 7.1 for the reference load for timing measurements.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI.
Rev. 1.20, 2007-06
27
11232006-QP6X-6EM0