HYB18T256161BF Datasheet, PDF (14/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
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Field Bits
Type¹⁾
TABLE 8
EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10_B)
Description
BA1 14
reg. addr., Bank Address [1]
1_B BA1 Bank Address
BA0 13
Bank Address [0]
0_B BA0 Bank Address
A
[12:8] w
Address Bus
00000_B A Address bits
SRF 7
w
Address Bus, High Temperature Self Refresh Rate for T_CASE > 85°C
0_B A7 disable
1_B A7 enable ²⁾
A
[6:3] w
Address Bus
0000_B A Address bits
Partial Self Refresh for 4 banks
PASR [2:0] w
Address Bus, Partial Array Self Refresh for 4 Banks³⁾
000_B PASR0 Full Array
001_B PASR1 Half Array (BA[1:0]=00, 01)
010_B PASR2 Quarter Array (BA[1:0]=00)
011_B PASR3 Not defined
100_B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101_B PASR5 Half array (BA[1:0]=10, 11)
110_B PASR6 Quarter array (BA[1:0]=11)
111_B PASR7 Not defined
1) w = write only
2) When DRAM is operated at 85°C ≤ T_Case £ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if t_REF conditions are met and no Self Refresh command is issued
Rev. 1.20, 2007-06
14
11232006-QP6X-6EM0