HYB18T256161BF Datasheet, PDF (28/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
5.7.2
AC Timing Parameters
List of Timing Parameters
Parameter
–20
Min.
Max.
DQ output access time from CK t_AC
/ CK
–450
+450
CAS A to CAS B command
t_CCD
2
—
period
CK, CK high-level width
t_CH
0.45
0.55
CKE minimum high and low t_CKE 3
—
pulse width
CK, CK low-level width
t_CL
Auto-Precharge write recovery t_DAL
+ precharge time
0.45
0.55
WR + t_RP —
Minimum time clocks remain
ON after CKE asynchronously
drops LOW
t_DELAY
t_IS + t_CK + ––
t_IH
DQ and DM input hold time
t_DH
145
––
(differential data strobe)
DQ and DM input hold time
t_DH1 -105
––
(single ended data strobe)
DQ and DM input pulse width t_DIPW 0.35
—
(each input)
DQS output access time from t_DQSCK –450
CK / CK
+450
DQS input low (high) pulse
t_DQSL,H 0.35
—
width (write cycle)
DQS-DQ skew (for DQS &
t_DQSQ —
450
associated DQ signals)
Write command to 1st DQS
latching transition
t_DQSS WL –
0.25
WL +
0.25
DQ and DM input setup time t_DS
20
(differential data strobe)
DQ and DM input setup time t_DS1
(single ended data strobe)
-105
DQS falling edge hold time
t_DSH 0.2
—
from CK (write cycle)
DQS falling edge to CK setup t_DSS 0.2
—
time (write cycle)
Clock half period
t_HP
MIN. (t_CL,
t_CH)
–25
Min.
–500
TABLE 29
Timing Parameter by Speed Grade
Max.
–28
Min.
Max.
Notes¹⁾
2)3)4)5)6)
+500
–550
+550
ps
2
—
0.45
0.55
3
—
0.45
0.55
WR + t_RP —
t_IS + t_CK + ––
t_IH
250
––
2
—
0.45
0.55
3
—
0.45
0.55
WR + t_RP —
t_IS + t_CK + ––
t_IH
275
––
t_CK
t_CK
t_CK
t_CK
t ⁷⁾¹⁸⁾
CK
ns ⁸⁾
ps ⁹⁾
0
––
25
––
ps ⁹⁾
0.35
–500
—
+500
0.35
–550
—
+550
t_CK
ps ⁹⁾
0.35
—
—
450
0.35
—
—
450
t_CK
ps ¹⁰⁾
WL –
0.25
125
0
WL +
0.25
––
––
WL –
0.25
150
25
WL +
0.25
––
––
t_CK
ps ⁹⁾
ps ⁹⁾
0.2
—
0.2
—
MIN. (t_CL,
t_CH)
0.2
—
0.2
—
MIN. (t_CL,
t_CH)
t_CK
t_CK
11)
Rev. 1.20, 2007-06
28
11232006-QP6X-6EM0