HYB18T256161BF Datasheet, PDF (21/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at V_REF.
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS signals are internally disabled and
don’t care.
Symbol
V_IH(dc)
V_IL(dc)
V_IH(ac)
V_IL(ac)
Parameter
DC input logic high
DC input low
AC input logic high
AC input low
Min.
V_REF + 0.125
–0.3
V_REF + 0.250
—
TABLE 20
DC & AC Logic Input Levels
Max.
Units
V_DDQ + 0.3
V
V_REF – 0.125
V
—
V
V_REF – 0.250
V
TABLE 21
Single-ended AC Input Test Conditions
Symbol
Condition
Value
Unit
Notes
V_REF
V_SWING.MAX
SLEW
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
0.5 x V_DDQ
1.0
1.0
V
1)
V
1)
V / ns
2)3)
1) Input waveform timing is referenced to the input signal crossing through the V_REF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from V_IH(ac).MIN to V_REF for rising edges and the range from V_REF to
V_IL(ac).MAX for falling edges as shown in Figure 2
3) AC timings are referenced with input waveforms switching from V_IL(ac) to V_IH(ac) on the positive transitions and V_IH(ac) to V_IL(ac) on the negative
transitions.
Rev. 1.20, 2007-06
21
11232006-QP6X-6EM0