 English |
|
|
|
|
|
|
|
| HYB18T256161BF Datasheet, PDF (22/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM | |||
| |||
| ◁ |
Internet Data Sheet
HYB18T256161BFâ20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
6 37 ) . ' -! 8
D E LT A 4&
& A LL IN G 3L E W 62 % &
6 ), A C M A X
D E LT A 4&
FIGURE 2
Single-ended AC Input Test Conditions Diagram
D E LT A 42
6$ $ 1
6) ( A C M IN
6) ( D C M IN
62 %&
6) , D C M AX
6) , A C M AX
63 3
2 IS IN G 3 LE W 6 )( A C M I N
62 % &
D E LT A 42
TABLE 22
Differential DC and AC Input and Output Logic Levels
Symbol Parameter
Min.
Max.
Unit Notes
VIN(dc)
DC input signal voltage
â0.3
VDDQ + 0.3
â
1)
VID(dc)
DC differential input voltage
0.25
VDDQ + 0.6
â
2)
VID(ac)
AC differential input voltage
0.5
VDDQ + 0.6
V
3)
VIX(ac)
AC differential cross point input voltage 0.5 Ã VDDQ â 0.175
0.5 Ã VDDQ + 0.175
V
4)
VOX(ac)
AC differential cross point output voltage 0.5 Ã VDDQ â 0.125
0.5 Ã VDDQ + 0.125
V
5)
1) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
2) VID(dc) specifies the input differential voltage VTRâ VCP required for switching. The minimum value is equal to VIH(dc) â VIL(dc).
3) VID(ac) specifies the input differential voltage VTR â VCP required for switching. The minimum value is equal to VIH(ac) â VIL(ac).
4) The value of VIX(ac) is expected to equal 0.5 Ã VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 Ã VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
6 4 2
6 ) $
6 #0
Rev. 1.20, 2007-06
11232006-QP6X-6EM0
FIGURE 3
Differential DC and AC Input and Output Logic Levels Diagram
6 $$ 1
# R O S S I N G 0 O I N T
6 ) 8 O R 6 / 8
22
6 3 3 1
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese