HYB18T256161BF Datasheet, PDF (17/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

4
Truth Tables
Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 12
Command Truth Table
Function
CKE
Previous Current
Cycle Cycle
CS RAS
CAS WE BA0 A[12:11] A10 A[9:0]
BA1
Note¹⁾²⁾³⁾
(Extended) Mode Register Set H
Auto-Refresh
H
Self-Refresh Entry
H
Self-Refresh Exit
L
H
LL
L L BA OP Code
4)5)
H
LL
L HX X
XX
4)
L
LL
L HX X
XX
4)6)
H
HX
X XX X
XX
4)6)7)
Single Bank Precharge
H
Precharge all Banks
H
Bank Activate
H
Write
H
Write with Auto-Precharge
H
Read
H
Read with Auto-Precharge H
No Operation
H
Device Deselect
H
Power Down Entry
H
LH
HH
H
LL
H L BA X
LX
4)5)
H
LL
H LX X
HX
4)
H
LL
H H BA Row Address
4)5)
H
LH
L
L BA Column L Column ⁴⁾⁵⁾⁸⁾
H
LH
L
L BA Column H Column ⁴⁾⁵⁾⁸⁾
H
LH
L
H BA Column L Column ⁴⁾⁵⁾⁸⁾
H
LH
L
H BA Column H Column ⁴⁾⁵⁾⁸⁾
X
LH
H HX X
XX
4)
X
HX
X XX X
XX
4)
L
HX
X XX X
XX
4)9)
Power Down Exit
LH
HH
L
H
HX
X XX X
XX
4)9)
LH
HH
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register.
6) V_REF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements.
Rev. 1.20, 2007-06
17
11232006-QP6X-6EM0