HYB18T256161BF Datasheet, PDF (7/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
Ball#
B3
F3
Name
UDM
LDM
Power Supplies
A9,C1,C3,C7,C9
A1
A7,B2,B8,D2,D8
A3,E3
Power Supplies
J2
E9, G1, G3, G7, G9
J1
E1, J9, M9, R1
E7, F2, F8, H2, H8
J7
A3, E3,J3,N1,P9
Not Connected
A2, E2, R3, R7, R8, L1
Other Balls
K9
V_DDQ
V_DD
V_SSQ
V_SS
V_REF
V_DDQ
V_DDL
V_DD
V_SSQ
V_SSDL
V_SS
NC
ODT
Ball Type Buffer Type Function
I
SSTL
Data Mask Upper/Lower Byte
I
SSTL
Note: LDM and UDM are the input mask signals and
control the lower or upper bytes.
PWR
–
PWR
–
PWR
–
PWR
–
I/O Driver Power Supply
Power Supply
I/O Driver Power Supply
Power Supply
AI
–
PWR
–
PWR
–
PWR
–
PWR
–
PWR
–
PWR
–
I/O Reference Voltage
I/O Driver Power Supply
Power Supply
Power Supply
I/O Driver Power Supply
Power Supply
Power Supply
NC
–
Not Connected
I
SSTL
On-Die Termination Control
Note: ODT is applied to each DQ, UDQS, UDQS,
LDQS, LDQS, UDM and LDM signal. An EMRS(1)
control bit enables or disables the ODT
functionality.
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Description
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
TABLE 3
Abbreviations for Ball Type
Rev. 1.20, 2007-06
7
11232006-QP6X-6EM0