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HYB18T256161BF Datasheet, PDF (33/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM
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Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data
bus inputs are floating.
Operating Bank Interleave Read Current
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK =
tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address
bus inputs are stable during deselects; Data bus is switching.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized.
3) IDD parameter are specified with ODT disabled.
4) Data Bus consists of DQ, DM, DQS, DQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for IDD: see Table 32
6) Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7..
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Note
1)2)3)4)5)6)
1)2)3)4)5)6)7)
Parameter
LOW
HIGH
STABLE
FLOATING
SWITCHING
Description
TABLE 32
Definition for IDD
defined as VIN ≤ VIL(ac).MAX
defined as VIN ≥ VIH(ac).MIN
defined as inputs are stable at a HIGH or LOW level
defined as inputs are VREF = VDDQ / 2
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
Speed Grade
Symbol
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
Rev. 1.20, 2007-06
11232006-QP6X-6EM0
–20
–25
-28
TABLE 33
IDD Specification
Unit
Note
typ.
typ.
typ.
92
81
77
mA
99
89
85
mA
4
4
4
mA
46
41
38
mA
40
38
35
mA
30
28
27
mA
1)
5
5
5
mA
2)
52
47
43
mA
166
153
145
mA
189
163
149
mA
127
119
115
mA
5
5
5
mA
3)
33
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