HYB18T256161BF Datasheet, PDF (18/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 13
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State¹⁾
CKE
Previous Cycle⁶⁾
(N-1)
Current Cycle⁶⁾
(N)
Command (N)²⁾³⁾RAS,
CAS, WE, CS
Action (N)²⁾
Note⁴⁾⁵⁾
Power-Down
L
L
Self Refresh
L
L
Bank(s)Active H
All Banks Idle H
H
Any State other H
than listed above
L
X
Maintain Power-Down
7)8)11)
H
DESELECT or NOP Power-Down Exit
7)9)10)11)
L
X
Maintain Self Refresh
8)11)12)
H
DESELECT or NOP Self Refresh Exit
9)12)13)14)
L
DESELECT or NOP Active Power-Down Entry
7)9)10)11)15)
L
DESELECT or NOP Precharge Power-Down Entry ^9)10)11)15)
L
AUTOREFRESH
Self Refresh Entry
7)11)14)16)
H
Refer to the Command Truth Table
17)
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh
requirements
8) “X” means “don’t care (including floating around V_REF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) t_CKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of t_IS + 2×t_CKE + t_IH.
12) V_REF must be maintained during Self Refresh operation.
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read
commands may be issued only after t_XSRD (200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or
Refresh operations are in progress.
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
Name (Function)
Write Enable
Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
TABLE 14
Data Mask (DM) Truth Table
DM
DQs
Note
L
Valid
1)
H
X
1)
Rev. 1.20, 2007-06
18
11232006-QP6X-6EM0