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HYB18T256161BF Datasheet, PDF (29/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM
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Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
Parameter
–20
Min.
Max.
Data-out high-impedance time tHZ
—
from CK / CK
tAC.MAX
Address and control input hold tIH
525
time
Address and control input pulse tIPW 0.6
—
width
(each input)
Address and control input setup tIS
400
time
DQ low-impedance time from tLZ(DQ) 2 × tAC.MIN tAC.MAX
CK / CK
DQS low-impedance from CK / tLZ(DQS) tAC.MIN
CK
tAC.MAX
Mode register set command tMRD 2
—
cycle time
OCD drive mode output delay tOIT
Data output hold time from
tQH
DQS
0
12
tHP–tQHS —
Data hold skew factor
tQHS
—
600
Average periodic refresh
tREFI
—
7.8
Interval
—
3.9
Auto-Refresh to Active/Auto- tRFC 75
—
Refresh command period
Read preamble
Read postamble
Active bank A to Active bank B
command period
tRPRE
tRPST
tRRD
0.9
0.40
7.5
1.1
0.60
—
Internal Read to Precharge
tRTP
7.5
—
command delay
Write preamble
Write postamble
Write recovery time for write
without Auto-Precharge
tWPRE
tWPST
tWR
0.35 x tCK —
0.40
0.60
13
—
Write recovery time for write WR tWR/tCK
with Auto-Precharge
Internal Write to Read
command delay
tWTR 7.5
—
Exit power down to any valid tXARD 2
—
command
(other than NOP or Deselect)
Exit active power-down mode tXARDS 10 – AL —
to Read command (slow exit,
lower power)
–25
Min.
—
575
0.6
Max.
tAC.MAX
—
—
450
—
2 × tAC.MIN tAC.MAX
tAC.MIN
tAC.MAX
2
—
0
12
tHP–tQHS —
—
600
—
7.8
—
3.9
75
—
0.9
1.1
0.40
0.60
7.5
—
7.5
—
0.35 x tCK —
0.40
0.60
15
—
tWR/tCK
7.5
—
2
—
8 – AL —
–28
Min.
—
625
0.6
Max.
tAC.MAX
—
—
500
—
2 × tAC.MIN tAC.MAX
tAC.MIN
tAC.MAX
2
—
0
12
tHP–tQHS —
—
600
—
7.8
—
3.9
75
—
0.9
1.1
0.40
0.60
7.5
—
7.5
—
0.35 x tCK —
0.40
0.60
15
—
tWR/tCK
7.5
—
2
—
7 – AL —
Notes1)
2)3)4)5)6)
ps 12)
ps
tCK
ps
ps 12)
ps 12)
tCK
ns
ps
μs 13)14)
μs 13)15)
ns 16)
tCK 12)
tCK 12)
ns 14)17)
ns
tCK
tCK 17)
ns
tCK 18)
ns 19)
tCK 20)
tCK 20)
Rev. 1.20, 2007-06
29
11232006-QP6X-6EM0
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