HYB18T256161BF Datasheet, PDF (20/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

Internet Data Sheet
5.2
DC Characteristics
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
Symbol
Parameter
Rating
TABLE 17
Recommended DC Operating Conditions (SSTL_18)
Unit Notes
Min.
Typ.
Max.
V_DD
Supply Voltage
1.7
1.8
1.9
V
1)2)
V_DDDL
Supply Voltage for DLL
1.7
1.8
1.9
V
1)2)
V_DDQ
Supply Voltage for Output
1.7
1.8
1.9
V
1)2)
V_REF
Input Reference Voltage
0.49 × V_DDQ
0.5 × V_DDQ
0.51 × V_DDQ
V
3)4)
V_TT
Termination Voltage
V_REF – 0.04
V_REF
V_REF + 0.04
V
5)
1) HYB18T256161BF–20/25/28
2) V_DDQ tracks with V_DD, V_DDDL tracks with V_DD. AC parameters are measured with V_DD, V_DDQ and V_DDDL tied together.
3) The value of V_REF may be selected by the user to provide optimum noise margin in the system. Typically the value of V_REF is expected to
be about 0.5 × V_DDQ of the transmitting device and V_REF is expected to track variations in V_DDQ.
4) Peak to peak ac noise on V_REF may not exceed ± 2% V_REF (dc)
5) V_TT is not applied directly to the device. V_TT is a system supply for signal termination resistors, is expected to be set equal to V_REF, and
must track variations in die dc level of V_REF.
TABLE 18
ODT DC Electrical Characteristics
Parameter / Condition
Symbol
Min.
Nom. Max.
Unit
Note
Termination resistor impedance value for
Rtt1(eff)
60
75
90
Ω
1)
EMRS(1)[A6,A2] = [0,1]; 75 Ohm
Termination resistor impedance value for
EMRS(1)[A6,A2] =[1,0]; 150 Ohm
Rtt2(eff)
120
150
180
Ω
1)
Deviation of V_M with respect to V_DDQ / 2
delta V_M
–6.00 —
+ 6.00
%
2)
1) Measurement Definition for Rtt(eff): Apply V_IH(ac) and V_IL(ac) to test pin separately, then measure current I(V_IHac) and I(V_ILac) respectively.
Rtt(eff) = (V_IH(ac) – V_IL(ac)) /(I(V_IHac) – I(V_ILac)).
2) Measurement Definition for V_M: Turn ODT on and measure voltage (V_M) at test pin (midpoint) with no load: delta V_M = ((2 x V_M / V_DDQ) –
1) x 100%
Symbol Parameter / Condition
IIL
Input Leakage Current; any input 0 V < VIN < V_DD
IOL
Output Leakage Current; 0 V < VOUT < V_DDQ
1) all other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS are disabled and ODT is turned off
TABLE 19
Input and Output Leakage Currents
Min.
Max.
Unit
Notes
–2
+2
μA
1)
–5
+5
μA
2)
Rev. 1.20, 2007-06
20
11232006-QP6X-6EM0