HYB18T256161BF Datasheet, PDF (11/40 Pages) Qimonda AG – 256-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T256161BF–20/25/28
256-Mbit Double-Data-Rate-Two SDRAM
Field Bits Type¹⁾
Description
BT
3
w
BL
[2:0] w
Burst Type
0_B BT Sequential
1_B BT Interleaved
Burst Length
Note: All other bit combinations are illegal.
010_B BL 4
011_B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing t_WR (in ns) by t_CK (in ns) and
rounding up to the next integer: WR [cycles] ≥ t_WR (ns) / t_CK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue t_WR timing WR_MIN is determined by t_CK.MAX and WR_MAX is determined by t_CK.MIN.
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ZZZZZZZ
Field
BA1
BA0
Qoff
A11
DQS
Bits Type¹⁾
14 reg. addr.
13
12 w
11 w
10 w
Description
TABLE 7
Extended Mode Register Definition (BA[1:0] = 01_B)
Bank Address [1]
0_B BA1 Bank Address
Bank Address [0]
1_B BA0 Bank Address
Output Disable
0_B QOff Output buffers enabled
1_B QOff Output buffers disabled
Address Bus [11]
0_B A11 Address bit 11
Complement Data Strobe (DQS Output)
0_B DQS Enable
1_B DQS Disable
Rev. 1.20, 2007-06
11
11232006-QP6X-6EM0