PDI1394L11 Datasheet, PDF (9/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
12.3.2 Write accesses
To write to an internal register the host interface must collect the 4
byte values into a 32 bit value and then write the result to the target
register in a single clock tick. This requires a register to hold the 32
bit value being compiled until it is ready to be written to the actual
target register. This temporary register inside the host interface is
called the write shadow register. During all write cycles address
lines HIF A0 and HIF A1 are used to select which of the 4 bytes of
the write shadow register is to be written with the value on the
CPU data bus. Only one byte can be written in a single write access
cycle.
This solution requires a control line to direct the host interface to
copy the write shadow register to the actual destination register
when ready, as well as the internal address of that register. The
destination register address is connected to input address lines
HIF A2..HIF A7, and the update control line to input address line
HIF A8. To let the host interface make the internal transfer the target
address must be presented on HIF A2..HIF A7 and HIF A8 must be
raised while executing a write access. The current value on the CPU
data bus will be stored in the write shadow register at the selected
byte (HIF A0, HIF A1) and the result will be copied into the specified
destination register.
MUX
8
32
CPU
TR
MUX
Q
Q
HIF A0..1
HIF A2..7
HIF A8
UPDATE/COPY CONTROL
REGISTERS
32
SV00804
NOTES:
1. It is not required to write all 4 bytes of a register: those bytes that are either reserved (undefined) or don’t care do not have to be written in
which case they will be assigned the value that was left in the corresponding byte of the write shadow register from a previous write
access. For example, to acknowledge an interrupt for the isochronous receiver (external address 0x04C), a single byte write to location
0x100+(0x4C)+3 = 0x14F is sufficient. The value 256 represents setting HIF A8=1. The host interface cannot directly access the FIFOs, but
instead reads from/writes into a transfer register (shown as TR in the Figures above). Data is moved between FIFO and TR by internal logic
as soon as possible without CPU intervention.
2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by
other means, for example a combinatorial circuit that activates the update control line whenever a write access is done for byte 3. This
makes the internal updating automatic for quadlet writing.
3. Writing the bytes of the read shadow register can be done in any order and as often as needed (new writes simply overwrite the old value).
1997 Oct 21
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