PDI1394L11 Datasheet, PDF (29/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
Bit 10:
Bit 9:
Bit 5:
Bit 4:
Bit 3..0:
R/W Cycle Source: When asserted, the cycle_count field increments and the cycle_offset field resets for each positive
transition of CYCLEIN. When deasserted, the cycle count field increments when the cycle_offset field rolls over.
R/W Cycle Timer Enable: When asserted, the cycle offset field increments.
R
Root: Indicates this device is the root on the bus. This automatically updates after the self_ID phase.
R
Busy Flag: The type of busy acknowledge which will be sent next time an acknowledge is required. 0 = Busy A,
1 = Busy B (only meaningful during a dual-phase busy/retry operation).
R
AT acknowledge received: The last acknowledge received by the transmitter in response to a packet sent from the
transmit-FIFO interface while the ATF is selected (diagnostic purposes).
13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008
The Link/Phy Interrupt Acknowledge register indicates various status and error conditions in the Link and Phy which can be programmed to
generate an interrupt. The interrupt enable register (LNKPHYINTE) is a mirror of this register. Acknowledgment of an interrupt is accomplished
by writing a ‘1’ to a bit in this register that is set. This action reset the bit indication to a ‘0’. Writing a ‘1’ to a bit that is already “0” will have no
effect on the register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00274
Reset Value 0x00000000
Bit 18:
R/W Command Reset Received: A write request to RESET-START has been received.
Bit 17:
R/W Fair Gap: The serial bus has been idle for a fair-gap time (called subaction gap in the IEEE 1394 specification).
Bit 16:
R/W Arbitration Reset Gap: The serial bus has been idle for an arbitration reset gap.
Bit 15:
R/W Phy Chip Int: The Phy chip has signaled an interrupt through the Phy interface.
Bit 14:
R/W Phy Register Information Received: A register has been transferred by the Physical Layer device into the Link.
Bit 13:
R/W Phy Reset Started: A Phy-layer reconfiguration has started. This interrupt clears the ID valid bit. (Called Bus Reset
in the IEEE 1394 specification).
Bit 12:
R/W Transmitter Ready: The transmitter is idle and ready.
Bit 11:
R/W Receiver has Data: The receiver has confirmed data to the receiver response/request FIFO. Used for diagnostic
purposes only.
Bit 10:
R/W Isochronous Transmitter is Stuck: The transmitter has detected invalid data at the transmit-FIFO interface when the
ITF is selected.
Bit 9:
R/W Asynchronous Transmitter is Stuck: The transmitter expected start of new async packet in queue, but found other
data (out of sync with user). Reset to clear.
Bit 8:
R/W Busy Acknowledge Sent by Receiver: The receiver was forced to send a busy acknowledge to a packet addressed
to this node because the receiver response/request FIFO overflowed.
Bit 7:
R/W Header Error: The receiver detected a header CRC error on an incoming packet that may have been addressed to
this node.
Bit 6:
R/W Transaction Code Error: The transmitter detected an invalid transaction code in the data at the transmit FIFO
interface.
Bit 5:
R/W
Cycle Timed Out. ISOCH cycle lasted more than 125µs from Cycle-Start to Fair Gap: Disables cycle master function
Bit 4:
R/W Cycle Second incremented: The cycle second field in the cycle-timer register incremented. This occurs
approximately every second when the cycle timer is enabled.
Bit 3:
R/W Cycle Started: The transmitter has sent or the receiver has received a cycle start packet.
Bit 2:
R/W Cycle Done: A fair gap has been detected on the bus after the transmission or reception of a cycle start packet. This
indicates that the isochronous cycle is over; Note: Writing a value of ‘0’ to the bit has no effect.
Bit 1:
R/W Cycle Pending: Cycle pending is asserted when cycle timer offset is set to zero (rolled over or reset) and stays
asserted until the isochronous cycle has ended.
Bit 0:
R/W Cycle Lost: The cycle timer has rolled over twice without the reception of a cycle start packet. This only occurs when
cycle master is not asserted.
1997 Oct 21
29