PDI1394L11 Datasheet, PDF (38/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
13.3.3 Asynchronous Transmit Request Next (TX_RQ_NEXT) – Base Address: 0x088
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_RQ_NEXT
Bit 31..0:
W
TX_RQ_NEXT: First/middle quadlet of packet for transmitter request queue (write only).
Writing this register will clear the TREQQWR flag until the quadlet has been written to its queue.
13.3.4 Asynchronous Transmit Request Last (TX_RQ_LAST) – Base Address: 0x08C
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_RQ_LAST
Bit 31..0:
W
TX_RQ_LAST: Last quadlet of packet for transmitter request queue (write only).
Writing this register will clear the TREQQWR flag until the quadlet has been written to its queue.
13.3.5 Asynchronous Transmit Response Next (TX_RP_NEXT) – Base Address: 0x090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_RP_NEXT
Bit 31..0:
W
TX_RP_NEXT: First/middle quadlet of packet for transmitter response queue (write only).
Writing this register will clear the TRSPQWR flag until the quadlet has been written to its queue.
13.3.6 Asynchronous Transmit Response Last (TX_RP_LAST) – Base Address: 0x094
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_RP_LAST
Bit 31..0:
W
TX_RP_LAST: Last quadlet of packet for transmitter response queue (write only).
Writing this register will clear the TRSPQWR flag until the quadlet has been written to its queue.
SV00293
SV00294
SV00295
SV00296
1997 Oct 21
38