PDI1394L11 Datasheet, PDF (7/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
11.1 Buffer Memory Sizes
BUFFER MEMORY
Asynchronous Receive Transaction Response FIFO
Asynchronous Receive Transaction Request FIFO
Asynchronous Transmit Transaction Response FIFO
Asynchronous Transmit Transaction Request FIFO
AV Transmit/Receive Buffer
SIZE
(Quadlets)
64
64
64
64
1024
12.0 FUNCTIONAL DESCRIPTION
12.1 Overview
The PDI1394L11 is an IEEE 1394–1995 compliant link layer
controller. It provides a direct interface between a 1394 bus and
various MPEG–2 and DVC codecs. Via this interface, the AV Link
maps and unmaps these AV datastreams from these codecs onto
1394 isochronous bus packets. The AV Link also provides an 8051
compatible microcontroller interface for an attached host controller.
Through the host interface port, the host controller can configure the
AV layer for transmission or reception of AV datastreams. The host
interface port also allows the host controller to transmit and receive
1394 asynchronous data packets.
12.2 AV interface and AV layer
The AV interface and AV layer allow AV packets to be transmitted
from one node to another. The AV transmitter and receiver within the
AV layer perform all the functions required to pack and unpack AV
packet data for transfer over a 1394 network. Once the AV layer is
properly configured for operation, no further host controller service
should be required. The operation of the AV layer is half-duplex, i.e.,
the AV layer can either receive or transmit AV packets at a particular
time.
12.2.1 The AV Interface
The AV Link provides an 8 bit data path to the AV layer. The 8 bit
data path is designed with associated clock and control signals to be
compatible with various MPEG–2 and DVC codecs.
The AV interface port buffer, if so programmed, can time stamp
incoming AV packets. The AV packet data is stored in the embedded
memory buffer, along with its time stamp information. After the AV
packet has been written into the AV layer, the AV layer creates an
isochronous bus packet with the appropriate CIP header. The bus
packet along with the CIP header is transferred over the appropriate
isochronous channel/packet. The size and configuration of
isochronous data packet payload transmitted is determined by the
AV layer’s configuration registers accessible through the host
interface.
The AV interface port waits for the assertion for AVVALID and
AVSYNC. Note: Do not assert AVSYNC without AVVALID.
AVSYNC is aligned with the rising edge of AVCLK and the first byte
of data on AVDATA[7:0]. The duration of AVSYNC is one AVCLK
cycle. AVSYNC signals the AV layer that the transfer of an AV
packet has begun. At the time the AVSYNC is asserted, the AV layer
creates a new time stamp in the buffer memory. (This only happens
if so configured. The DVC format does not require these time
stamps). The time stamp is then transmitted as part of the standard
packet header. This allows the AV receiver to provide the AV packet
for output at the appropriate time.
When the DV video is enabled (via the format code of the CIP
header), the frame synchronization signal AVFSYNCIN is time
stamped and placed in the SYT field. The timestamp value is 3 cycle
times (duration of 125ms) in the future and is transmitted in the SYT
field of the current CIP header. On the receiver side, when the SYT
stamp matches the cycle timer register, a pulse is generated on the
AVFSYNCOUT output. The timing for AVFSYNCIN and
AVFSYNCOUT are independent of AV clock.
12.2.2 IEC 61883 International Standard
The PDI1394L11 is specifically designed to support the proposed
IEC61883 International Standard of Digital Interface for Consumer
Electronic Audio/Video Equipment. The IEC specification defines a
scheme for mapping various types of AV datastreams onto 1394
isochronous data packets. The standard also defines a software
protocol for managing isochronous connections in a 1394 bus called
Connection Management Protocol (CMP). It also provides a
framework for transfer of functional commands, called Function
Control Protocol (FCP).
12.2.3 CIP Headers
A feature of the IEC61883 International Standard is the definition of
Common Isochronous Packet (CIP) headers. These CIP headers
contain information about the source and type of datastream
mapped onto the isochronous packets.
The AV Layer supports the use of CIP headers. CIP headers are
added to transmitted isochronous data packets at the AV data
source. When receiving isochronous data packets, the AV layer
automatically analyzes their CIP headers. The analysis of the CIP
headers determines the method the AV layer uses to unpack the AV
data from the isochronous data packets.
The information contained in the CIP headers is accessible via
registers in the host interface.
(See IEC61883 International Standard of Digital Interface for
Consumer Electronic Audio/Video Equipment for more details on
CIP headers).
12.3 The host interface
The host interface allows an 8 bit CPU to access all registers and
the asynchronous packet queues. It is specifically designed for an
8051 microcontroller but can also be used with other CPUs. There
are 64 register addresses (for quadlet wide registers). To access
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