PDI1394L11 Datasheet, PDF (11/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
HIF CS_N
HIF RD_N
HIF WR_N
HIF A8
HIF A0..HIF A7
HIF D0..HIF D7
HIF CS_N
HIF RD_N
T_AS
T_AS
T_ACC
RSR_O
RSR_n
T_ACC
RSR_n
Figure 2. Read cycle signal timing (2 independent read cycles)
T_AS
SV00686
HIF WR_N
HIF A0..HIF A8
T_AS
<VALID ADDRESS>
<VALID ADDRESS>
HIF D0..HIF D7
<WRITE DATA>
<WRITE DATA>
Figure 3. Write cycle signal timing (2 independent write cycles)
SV00687
12.4 The Asynchronous Packet Interface
The PDI1394L11 provides an interface to asynchronous data
packets through the registers in the host interface. The format of the
asynchronous packets is specified in the following sections.
12.4.1 Reading an Asynchronous Packet
Upon reception of a packet, the packet data is stored in the
appropriate receive FIFO, either the Request or Response FIFO.
The location of the packet is indicated by either the RREQQQAV or
RRSPQAV status bit being set in the Asynchronous Interrupt
Acknowledge (ASYINTACK) register. The packet is transferred out
of the FIFO by successive reads of the Asynchronous Receive
Request (RREQ) or Asynchronous Receive Response (RRSP)
register. The end of the packet (the last quadlet) is indicated by
either the RREQQLASTQ or RRSPQLASTQ bit set in ASYINTACK.
Attempting to read the FIFO when either RREQQQAV bit or
RRSPQQAV bit is set to 0 (in the Asynchronous RX/TX interrupt
acknowledge (ASYINTACK) register) will result in a queue read
error.
12.4.2 Writing an Asynchronous Packet
An asynchronous packet intended for transmission is first stored in
the appropriate Transmitter FIFO. Once writing to the FIFO is
complete, the link layer controller arbitrates for the bus to transmit
the packet.
To generate an asynchronous packet, the first and next to last
quadlets of the packet must be written to the Asynchronous
Transmit Request Next (TX_RQ_NEXT) register, for request type
packets, or the Asynchronous Transmit Response Next
(TX_RP_NEXT) register, for response type packets. The last
quadlet of the packet is written to the Asynchronous Transmit
Request Last (TX_RQ_LAST) register, for request type packets, or
the Asynchronous Transmit Response Last (TX_RP_LAST)
register, for response type packets. After writing the last quadlet,
the packet is automatically queued by the AVlink layer controller for
transmission over the bus.
1997 Oct 21
11