PDI1394L11 Datasheet, PDF (43/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
16.3 PHY-Link Interface Critical Timings
SCLK
t_SCLKPER
50%
t_SUP
t_HP
PHY D[0:7], PHY CTL[0:1]
50%
50%
Figure 26. PHY D[0:7], PHY CTL[0:1] Input Setup and Hold Timing Waveforms
SV00695
SCLK
PHY D[0:7], PHY CTL[0:1], LREQ
50%
t_DP
50%
Figure 27. PHY D[0:7], PHY CTL[0:1], and LREQ Output-Delay Timing Waveforms
16.4 Host Interface Critical Timings
READ
t_AS
t_AS
HIF A[8:0]
VALID
t_CL
HIF CS_N
t_RP
HIF RD_N
HIF D[7:0]
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
t_ACC
t_AH
t_AH
t_CH
VALID
t_DH
SV00694
WRITE
HIF WR_N
t_WRP
HIF D[7:0]
VALID
t_DS
t_DH
Figure 28. Host Interface Timing Waveforms
SV00699
1997 Oct 21
43