PDI1394L11 Datasheet, PDF (32/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
Bit 3..2:
Bit 1:
Bit 0:
R/W PM: packing mode:
00 = variable sized bus packets, most generic mode.
01 = fixed size bus packets.
10 = MPEG–2 packing mode.
11 = No data, just CIP headers are transmitted.
R/W EN_FS:enable generation/insertion of SYT stamps (Time Stamps) in CIP header.
R/W Reset Isochronous Transmitter: causes transmitter to be reset when ‘1’. In order for synchronous reset of ITX to
work properly, the application must supply an AVCLK and ensure that the reset bit is kept (programmed) HIGH for
at least the duration of one AVCLK period. Failure to do so may cause the application interface of this module
to be improperly reset (or not reset at all).
13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024
The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. This information is
included in Common Isochronous Packet (CIP) header quadlet 1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBS
FN QPC
SV00280
Reset Value 0x00000000
Bit 10:
R/W SPH: Indicates that a 25-bit CYCTM based time stamp has to be inserted before each application packet.
Bit 11..13:
R/W QPC: Number of dummy quadlets to append to each source packet before it is divided into data blocks of the
specified size. The value QPC must be less than DBS and less than 2^FN.
Bit 14..15:
R/W FN: (Fraction Number) The encoding for the number of data blocks into which each source packet shall be divided
(00 = 1, 01 = 2, 10 = 4, 11 = 8).
Bit 16..23:
R/W DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.
13.2.3 Common Isochronous Transmit Packet Header Quadlet 2 (ITXHQ2) – Base Address: 0x028
The contents of this register are copied to the second quadlet of the CIP header and transmitted with each isochronous packet.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMT
FDF
SYT
SV00281
Reset Value 0x00000000
Bit 29..24:
R/W FMT: Value to be inserted in the FMT field in the AV header.
Bit 23..0:
R/W FDF/SYT: Value to be inserted in the FDF field. When the EN_FS bit in the Transmit Control and Status Register
(ITXPKCTL) is set (=1), the lower 16 bits of this register are replaced by an SYT stamp if a rising edge on
AVFSYNCIN has been detected or all ‘1’s if no such edge was detected since the previous packet. The upper 8 bits
of the register are sent as they appear in the FDF register. When the EN_FS bit in the Transmit Control and Status
Register is unset (=0), the full 24 bits can be set to any application specified value.
1997 Oct 21
32