PDI1394L11 Datasheet, PDF (10/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
12.3.3 Byte order
The bytes in each quadlet are numbered 0..3 from left (most
significant) to right (least significant) as shown in Figure 1.
To access a register at internal address N the CPU should use
addresses E:
E=4N
; to access the upper 8 bits of the register.
E = 4 N + 1 ; to access the upper middle 8 bits of the register.
E = 4 N + 2 ; to access the lower middle 8 bits of the register.
E = 4 N + 3 ; to access the lower 8 bits of the register.
12.3.4 Accessing the packet queues
Although entire incoming packets are stored in the receiver buffer
memory they are not randomly accessible. These buffers act like
fifos and only the frontmost (oldest) data quadlet entry is accessible
for reading. Therefore only one location (register address) is
allocated to each of the two receiver queues. Reading this location
returns the head entry of the queue, and at the same time removes
it from the queue, making the next stored data quadlet accessible.
With the current host interface such a read is in fact a move
operation of the data quadlet from the queue to the read shadow
register. Once the data is copied into the read shadow register it is
no longer available in the queue itself so the CPU should always
read all 4 bytes before attempting any other read access (be careful
with interrupt handlers for AVLink!).
A similar argument applies to the transmitter queues. Data cannot
be written arbitrarily, but only to the next available free location.
Since the transmitter needs to know when the packet is complete
(all data stored in memory, so that it may start the arbitration
process on the 1394 bus) two separate register locations are
reserved per transmitter queue: one to write all but the last packet
quadlet to, and one to write the last quadlet of every packet to.
Writing to any of these register locations stores the data in the
queue and makes the next memory location accessible for writing.
NOTE:
1. Because of the way it is implemented memory access is not
always immediate; consequently it may take some time before
the next data quadlet in the queue is accessible after reading or
writing the current one. Status flags are provided to the CPU to
indicate availability.
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE 0
BYTE 1
BYTE 2
BYTE 3
Figure 1. Byte order in quadlets as implemented in the host interface
SV00656
12.3.5 The CPU bus interface signals
The CPU interface is directly compatible with an 8051
microcontroller. It uses a separate HIF RD_N and HIF WR_N inputs
and a HIF CS_N chip select line, all of which are active LOW. There
are 9 address inputs (HIF A0..HIF A8) and 8 data in/out lines
HIF D0..HIF D7. An open drain HIF INT_N output is used to signal
interrupts to the CPU.
The CPU is not required to run at a clock that is synchronous to the
1394 base clock. The control signals will be resampled by the host
interface before being used internally.
An access through the host interface starts when HIF CS_N = 0 and
either HIF WR_N = 0 or HIF RD_N = 0. Typically the chip select
signal is derived from the upper address lines of the CPU (address
decode stage), but it could also be connected to a port pin of the
CPU to avoid the need for an external address decoder in very
simple CPU systems. When both HIF CS_N = 0 and HIF RD_N = 0
the host interface will start a read access cycle, so the cycle is
triggered at the falling edge of either HIF CS_N or HIF RD_N,
whichever is later.
Very shortly after the start of the cycle, the selected byte in the read
shadow register will be output (indicated in Figure 2 as RSR_O). If
HIF A8 is asserted then the target register value will be copied into
the read shadow register, leading to a new value RSR_n some time
later in the read cycle. If HIF A8 is LOW, then the read shadow
register will not change.
A write access starts when the later of HIF CS_N and HIF WR_N
becomes LOW (see Figure 3). Data is written to the shadow
register, following which, if HIF A8 is asserted, the shadow register
value is copied to the addressed register.
NOTES:
1. The time between the end of any access and the start of the next
access must be at least t_CH which needs to be greater than
(2 x SCLK).
2. When HIF A8 = 0 for either write or read access the address bits
HIF A2..HIF A7 are ignored.
3. If both HIF WR_N = 0 and HIF RD_N = 0 while HIF CS_N = 0,
then a write cycle takes place.
1997 Oct 21
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