PDI1394L11 Datasheet, PDF (22/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1110₂
0000₂
PHY packet first quadlet
Figure 20. PHY Packet Receive Format
SV00265
For PHY packets, there is a single following quadlet which is the first quadlet of the PHY packet. The check quadlet has already been verified
and is not included.
12.5.2.5 Transaction data confirmation formats
After a packet from one of the queues has been transmitted, the asynchronous transmitter assembles a confirmation (see Figure 21) which is
used to confirm the result of the transmission to the higher layers. Separate confirmations are assembled for request and response
transmissions. Request confirmations are written into the request queue and response confirmations are written into the response queue.
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destinationID
tLabel
00₂ 1000₂
conf
Figure 21. Request and response confirmation format
SV00821
Table 7. Confirmation codes
CODE¹
0
DESCRIPTION
Non-broadcast packet transmitted; addressed node returned no acknowledge.
1
Broadcast packet transmitted or non-broadcast packet transmitted; addressed node returned an acknowledge complete.
2
Non-broadcast packet transmited; addressed node returned an acknowledge pending.
4
Retry limit exceeded; destination node hasn’t accepted the non-broadcast packet within the maximum number of retries.
D₁₆
Acknowledge data error received (transaction complete).
E₁₆
Acknowledge type error received (transaction complete).
NOTE:
1. All other codes are reserved.
For every packet written in a transmitter queue by the CPU, there will be one confirmation written in the corresponding receiver queue by the AV
layer logic.
12.5.3 Interrupts
The PDI1394L11 provides a single interrupt line (HIF INT_N) for connection to a host controller. Status indications from four major areas of the
device are collected and ORed together to activate HIF INT_N. Status from four major areas of the device are collected in four status registers;
LNKPHYINTACK, ITXINTACK, IRXINTACK, and ASYINTACK. At this level, each individual status can be enabled to generate a chip-level
interrupt by activating HIF INT_N. To aid in determining the source of a chip-level interrupt, the major area of the device generating an interrupt
is indicated in the lower 4 bits of the GLOBCSR register. These bits are non-latching Read-Only status bits and do not need to be
acknowledged. To acknowledge and clear a standing interrupt, the bit in LNKPHYINTACK, ITXINTACK, IRXINTACK, or ASYINTACK causing
the interrupt status has to be written to a logic ‘1’; Note: Writing a value of ‘0’ to the bit has no effect.
1997 Oct 21
22