PDI1394L11 Datasheet, PDF (23/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
12.5.3.1 Determining and Clearing Interrupts
When responding to an interrupt event generated by the PDI1394L11, or operating in polled mode, the first register examined is the GLOBCSR
register. The least significant nibble contains interrupt status bits from general sections of the device; the link layer controller, the AV transmitter,
the AV receiver, and the asynchronous transceiver. The bits in GLOBCSR[3:0] are self clearing status bits. They represent the logical OR of all
the enabled interrupt status bits in their section of the AV Link Layer Controller.
Once an interrupt, or status is detected in GLOBCSR, the appropriate interrupt status register needs to be read, see the Interrupt Hierarchy
diagram for more detail. After all the interrupt indications are dealt with in the appropriate interrupt status register, the interrupt status indication
will automatically clear in the GLOBCSR.
All interrupt status bits in the various interrupt status registers are latching unless otherwise noted.
12.5.3.2 Interrupt Hierarchy
HIF INT_N
3 21 0
GLOBCSR (0x018)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LNKPHYINTACK (0x008)
7 6 543 21 0
IRXINTACK (0x04C)
6 543 21 0
ITXINTACK (0x02C)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYINTACK (0x0A0)
SV00271
1997 Oct 21
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