PDI1394L11 Datasheet, PDF (4/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
8.0 APPLICATION DIAGRAM
MPEG OR DVC
DECODER
AV
INTERFACE
PDI1394L11
AV LINK
DATA 8/
ADDRESS 9/
INTERRUPT & CONTROL
PHY–LINK
INTERFACE
PDI1394P11
PHY
1394 CABLE
INTERFACE
HOST CONTROLLER
9.0 PIN DESCRIPTION
9.1 Host Interface
PIN No.
PIN SYMBOL
14, 15, 16, 17,
18, 19, 20, 21, 22
HIF A[8:0]
1, 2, 3, 4, 7, 8, 9,
10
HIF D[7:0]
26
HIF WR_N
27
HIF RD_N
25
HIF CS_N
28
29
6, 13, 24, 32, 39,
45, 49, 64, 72, 78
5, 12, 23, 31, 38,
44, 50, 63, 73, 79
HIF INT_N
RESET_N
V_DD
GND
SV00268
I/O
NAME AND FUNCTION
I
Host Interface Address 0 through 8. Provides the host with a byte wide interface to internal
registers. See description of Host Interface for addressing rules.
I/O Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers.
Write enable. When asserted (LOW) in conjunction with HIF CS_N, a write to the PDI1394L11
internal registers is requested. (NOTE: HIF WR_N and HIF RD_N : if these are both LOW in
I conjunction with HIF CS_N, then a write cycle takes place. This can be used to connect
CPUs that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect
the R/W_N line to the HIF WR_N and tie HIF RD_N LOW.)
I
Read enable. When asserted (LOW) in conjunction with HIF CS_N, a read of the PDI1394L11
internal registers is requested.
I
Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control
and status registers.
Interrupt (active LOW). Indicates a interrupt internal to the PDI1394L11. Read the General
O Interrupt Register for more information. This pin is open drained and requires a 1KW pullup
resistor.
I Reset (active LOW). The asynchronous master reset to the PDI1394L11.
3.3V ± 0.3V power supply
Ground reference
1997 Oct 21
4