PDI1394L11 Datasheet, PDF (34/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
13.2.7 Isochronous Transmitter Memory Status (ITXMEM) – Base Address: 0x038
The AV Transmitter Memory Status register reports on the condition of the internal memory buffer used to store incoming AV data streams
before transmission over the 1394 bus.
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset Value 0x00000003
Bit 3:
R
ITXMF: memory is completely full, no storage available.
Bit 2:
R
ITXMAF: almost full, exactly one quadlet of storage available.
Bit 1:
R
ITXM5AV: at least 5 more quadlets of storage available.
Bit 0:
R
ITXME: memory bank is empty (zero quadlets stored).
13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) – Base Address: 0x040
SV00284
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BPAD
SV00285
Reset Value 0x00000041
AV Receiver Control Bits.
Bit 6:
R/W RMVUAP: Remove unreliable packets from memory, do not attempt delivery
Bit 5:
R
SPAV: Source packet available for delivery in buffer memory.
Bit 4:
R/W EN_IRX: Enable receiver operation. Value is only checked whenever a new bus packet arrives, so enable/disable
while running is ‘graceful’.
Bit 2..3:
R/W BPAD: Value indicating the amount of byte padding to be removed from the last data quadlet of each source
packet, from 0 to 3 bytes. This is in addition to quadlet padding as defined in IEC 61883 International Standard.
Bit 1:
R/W EN_FS: Enable processing of SYT stamps.
Bit 0:
R/W RST_IRX: causes the receiver to be reset when ‘1’. In order for synchronous reset of IRX to work properly, the
application must supply an AVCLK and ensure that the reset bit is kept (programmed) HIGH for at least the duration
of one AVCLK period. Failure to do so may cause the application interface of this module to be improperly reset (or
not reset at all).
13.2.9 Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044
This quadlet represents the last received header value when AV receiver is operating.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
DBS
FN QPC
SV00286
Reset Value 0x00000000
Bit 31..30:
R
E0: End of Header, F0: Format: Always set to 00 for first AV header quadlet
Bit 29..24
R
SID: Source ID, contains the node address of the sender of the isochronous data.
Bit 23.16:
R
DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.
Bit 15..14:
R
FN (Fraction Number): The encoding for the number of data blocks into which each source packet has been divided
(00 = 1, 01 = 2, 10 = 4, 11 = 8) by the transmitter of the packet.
Bit 13..11:
R
QPC: Number of dummy quadlets appended to each source packet before it was divided into data blocks of the
specified size.
1997 Oct 21
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