PDI1394L11 Datasheet, PDF (39/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RREQ
Reset Value 0x00000000
Bit 31..0:
R
RREQ:Quadlet of packet from receiver request queue (transfer register).
Reading this register will clear the RREQQQAV flag until the next received quadlet is available for reading.
13.3.8 Asynchronous Receive Response (RRSP) – Base Address: 0x09C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRSP
Reset Value 0x00000000
Bit 31..0:
R
RRSP:Quadlet of packet from receiver response queue (transfer register).
Reading this register will clear the RRSPQQAV flag until the next received quadlet is available for reading.
13.3.9 Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) – Base Address: 0x0A0
SV00297
SV00298
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset Value 0x00000000
Bit 31..17:
R/W
Unused bits read ‘0’
Bit 16:
R/W
RRSPQFULL: Receiver response queue did become full.
Bit 15:
R/W RREQQFULL: Receiver request queue did become full.
Bit 14:
R/W SIDQAV: Current quadlet in RREQ is selfID data.
Bit 13:
R/W RRSPQLASTQ: Current quadlet in RRSP is last quadlet of packet.
Bit 12:
R/W RREQQLASTQ: Current quadlet in RREQ is last quadlet of packet.
Bit 11:
R/W RRSPQRDERR: Receiver response queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access.
Bit 10:
R/W RREQQRDERR: Receiver request queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access.
Bit 9:
R/W RRSPQQAV: Receiver response queue quadlet available (in RRSP).
Bit 8:
R/W RREQQQAV: Receiver request queue quadlet available (in RREQ).
Bit 7:
R/W TIMEOUT: Split transaction response timeout.
Bit 6:
R/W RCVDRSP: Solicited response received (within timeout interval).
Bit 5:
R/W TRSPQFULL: Transmitter response queue did become full.
Bit 4:
R/W TREQQFULL: Transmitter request queue did become full.
Bit 3:
R/W TRSPQWRERR: Transmitter response queue write error (transfer error).
1997 Oct 21
39
SV00796