PDI1394L11 Datasheet, PDF (31/46 Pages) NXP Semiconductors – 1394 AV link layer controller

Philips Semiconductors
1394 AV link layer controller
Product specification
PDI1394L11
13.1.7 Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018
This register is the top level interrupt status register. If the external interrupt line is set, this register will indicate which major portion of the AV
Link generated the interrupt. There is no interrupt acknowledge required at this level. These bits auto clear when the interrupts in the
appropriate section of the device are cleared or disabled. Control of the AV transceiver is also provided by this register.
Bits 0 to 3 are used to identify which internal modules are currently generating an interrupt. After identifying the module, the appropriate register
in that module must be read to determine the exact cause of the interrupt.
NOTES
1. There can be more than one interrupt source active at the same time.
2. The HIF INT_N signal (pin 28) remains active as long as there is at least one more enabled active interrupt status bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00278
Reset Value 0x00010000
Bit 16:
R/W Transmit Mode: Control bit, a ‘1’ enables the AV transmitter. A ‘0’ enables the AV receiver. The register defaults to
‘1’ on reset. Also this bit directly controls the direction of the bi-directional pins of the AV interface.
Bit 11:
R/W Enables generation of external interrupt by asynchronous transmitter and receiver module (ASYTX/RX, bit 3) when
set (1). Disables such interrupts when clear (0) (regardless of ASYINTE contents).
Bit 10:
R/W Enables generation of external interrupt by the isochronous transmitter module (ITXINT, bit 2) when set (1).
Disables such interrupts when clear (0) (regardless of ITXINTE contents).
Bit 9:
R/W Enables generation of external interrupt by the isochronous receiver module (IRXINT, bit 1) when set (1). Disables
such interrupts when clear (0) (regardless of IRXINTE contents).
Bit 8:
R/W Enables generation of external interrupt by general link/phy module (LKPHYINT, bit 0) when set (1). Disables
such interrupts when clear (0) (regardless of LNKPHYINTE contents).
Bit 3:
R
Asynchronous Transmitter/ Receiver Interrupt: Interrupt source is in the Asynchronous Transmitter/ Receiver
Interrupt Acknowledge/Source register.
Bit 2:
R
AV Transmitter Interrupt: Interrupt source is in the AV Transmitter Interrupt Acknowledge/Source register.
Bit 1:
R
AV Receiver Interrupt: Interrupt source is in the AV Receiver Interrupt Acknowledge/Source register.
Bit 0:
R
Link-Phy Interrupt: Interrupt source is in the Link Phy Interrupt Acknowledge register.
13.2 AV (Isochronous) Transmitter and Receiver Registers
13.2.1 Isochronous Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020
This register allows the user to set up the appropriate AV packets from data entered into the AV interface. The packing and control parameters
(TRDEL, MAXBL, DBS, FN, QPC, and SPH) should never be changed while the transmitter is operating. The only exception to this is the
MAXBL parameter when in MPEG-2 packing mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRDEL
MAXBL
PM
SV00279
Reset Value 0x00000001
Bit 27..16:
R/W TRDEL: Transport delay. Value added to cycle timer to produce time stamps. Lower 4 bits add to upper
4 bits of cycle_offset, (Cycle Timer Register, CYCTM). Remainder adds to cycle_count field.
Bit 15..8:
R/W MAXBL: The (maximum) number of data blocks to be put in a payload.
Bit 4:
R/W EN_ITX: Enable receipt of new application packets and generation of isochronous bus packets in every cycle. This
bit also enables the Link Layer to arbitrate for the transmitter in each subsequent bus cycle. When this bit is disabled
(0), the current packet will be transmitted and then the transmitter will shut down.
1997 Oct 21
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