SAA8200HL Datasheet, PDF (38/71 Pages) NXP Semiconductors – Ensation Base integrated wireless audio baseband

Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
7.19.2.3 Soft start-up after reset
After a reset of the decimation filter and if bit EN_DBLIN (SADC_CTRL_DECI[21]) is a
logic 1, the output gain of the decimator is increased from mute to −63.5 dB and at a rate
of 0.5 dB per f_s period to 0 dB (dB linear) to avoid harsh audible plops. The time required
for a complete soft start-up if bit EN_DBLIN is a logic 1 for 128 f_s periods. This time is
without the time required if bit EN_DELAY_DBLIN (SADC_CTRL_DECI[21]) is a logic 1,
e.g. if bit EN_DBLIN and bit EN_DELAY_DBLIN are a logic 1, bit EN_DCFILTI and bit
EN_DCFILTO are logic 0 the total time required is (44 +128) f_s periods (see Table 18). The
decimator soft start-up function is illustrated in Figure 9.
Table 18: Required time after reset
EN_DELAY_DBLIN EN_DBLIN EN_DCFILTI
0
0
X
0
1
X
1
0
0
1
0
1
1
0
X
1
1
0
1
1
1
1
1
X
EN_DCFILTO Required time
X
0s
X
128 periods of f_s
0
44 periods of f_s
0
17066 periods of f_s
1
67473 periods of f_s
0
(44 + 128) periods of f_s
0
(17066 + 128) periods of f_s
1
(67473 + 128) periods of f_s
EN_DCFILTI = 0
EN_DCFILTO = 0
RESET = 0
ENABLE_DBLIN = 1
ABLE_DELAY_DBLIN = 1
44
periods of f_s
128
periods of f_s
DOUT
(analog representation)
For readability, the parallel output data is shown in its analog representation.
Fig 9. Soft start-up function
001aab463
7.19.2.4 Signal polarity
The polarity of the output signal is controlled by bit EN_POL_INV
(SADC_CTRL_DECI[17]). When this bit is enabled, the polarity of the output data is
inverted.
SAA8200HL_2
Preliminary data sheet
Rev. 02 — 17 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
38 of 71