SAA8200HL Datasheet, PDF (29/71 Pages) NXP Semiconductors – Ensation Base integrated wireless audio baseband

Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
7.11 SPDIF inputs
One input is provided, this SPDIF input is fed through a bit slicer which is used to
re-generate the bitstream signal, allowing for a higher robustness of the link.
The SPDIF input hardware consists of a series connection of a bit slicer, which is an
analog module, the SPDIF decoder and a SPDIF input block. This SPDIF input block is
almost the same as the SPDIF input blocks which are connected to the SPDIF input pads.
The only difference between the SPDIF input blocks is that the input format of the SPDIF
input block is fixed in hardware to accept only SPD3 format.
The SPDIF decoder is running on a dedicated clock, which should lie between 36 MHz
and 69 MHz. In this clock domain signal SPD3_BCK is generated, which is treated by the
I²S-bus input block as a bit clock. This bit clock is again routed via the CGU to be able to
insert the test clock during test mode. The SPDIF input decoder latches it’s output data on
the negative edge of SPD3_BCK. The I²S-bus input will latch the data on the positive
edge of the bit clock. This guarantees reliable data transfer even though the clock is
delayed by the path through the CGU.
The word select from the SPDIF input decoder is routed to the CGU. This makes it
possible to lock the audio PLL to the incoming SPDIF stream.
7.12 I²S-bus
The supported audio formats for the control modes are:
• I²S-bus
• LSB-justified, 16-bit
• LSB-justified, 18-bit
• LSB-justified, 20-bit
• LSB-justified, 24-bit (only for the output interface).
The bit clock BCK can be up to 128f_s, or in other words the BCK frequency is 128 times
the WS frequency or less: f_BCK ≤ 128f_WS.
SAA8200HL_2
Preliminary data sheet
Rev. 02 — 17 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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