SAA8200HL Datasheet, PDF (32/71 Pages) NXP Semiconductors – Ensation Base integrated wireless audio baseband

Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
7.14 DMA controller
The purpose of the external DMA controller block is to share the external DMA channel of
the EPICS7B DSP sub system between a number of external peripherals: the serial radio
interface, the Reed-Solomon codec, the I²C-bus M/S and MPI. The controller needs to
arbitrate between those blocks.
Features:
• Interface between external DMA hardware blocks and the EPICS7B DSP subsystem
• Allows hardware blocks to read/write directly to X-, Y-, P-memory and to internal DSP
registers.
• Supports single word memory access and memory block transfers of programmable
length.
• Signals block transfer ready per requesting hardware device
• Arbiter priority schedule between four requesting sources (SRI, I²C-bus M/S, RSC
and MPI).
• Each requesting hardware block has its own start address and block transfer size
register
• Dispatches acknowledges and keeps track of progress of each block transfer
• Signals block transfer ready per requesting hardware device.
7.15 I/O configuration
The input/output configuration (IOCONF) is designed to provide developers a set of
registers. This can be used for configuration of various on chip components especially a
pad multiplexer.
The IOCONF block is used to provide individual control and visibility for a set of pads. In
conjunction with a set of pad multiplexers, individual pads can be switched either in
normal operation mode, or in GPIO mode. In GPIO mode, a pad is fully controllable.
Through the IOCONF, individual pad levels can be observed in both normal and GPIO
modes.
Functional pads can be grouped into function blocks.
All output values in a function block can be set simultaneously by accessing a single
register. Changing modes for all pads within a function block requires at most two register
access. All input values in a function block can be read simultaneously by accessing a
single register. Input values are not registered and always read directly from the pad’s
input driver regardless of the mode of the pad.
For each function block there are two registers holding the control mode. MODE bit 1
leaves the IOCONF inverted as it is intended to be used as inverted (output-) enable.
Each register can be written and read, has configurable pad names per bit (maximum 32)
and provides set and clear access methods (SET/CLEAR bit when ‘1’), and configurable
reset value. Configurable pad names are provided in order to enhance readability and
consistency of both HDL and generated C header file.
SAA8200HL_2
Preliminary data sheet
Rev. 02 — 17 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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