SAA8200HL Datasheet, PDF(20/71 Page) NXP Semiconductors – Ensation Base integrated wireless audio baseband

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SAA8200HL Datasheet, PDF (20/71 Pages) NXP Semiconductors – Ensation Base integrated wireless audio baseband

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Philips Semiconductors

SAA8200HL

Ensation Base integrated wireless audio baseband

Table 11: VPB0 bridge interface description â¦continued

Base address Offset Key

Description

0x02B8 ESR_CR_CLK_OUT1

enable fraction divider for crystal output 1 from pad

0x02BC ESR_CR_CLK_OUT2

enable fraction divider for crystal output 2 from pad

0x02C0 ESR_SRI_CHCLK

enable fraction divider for SRI channel clock

0x02C4 BCR_LP0

base control register for system PLL clock

0x02C8 BCR_HP0

base control register for audio PLL clock

0x2CC FDC_SPD_SYSCLK

fractional divider control for system clock

0x2D0 FDC_SYSCLK_DIV4

0x02D4 FDC_UART_UCLK

fractional divider control for 0.25 Ã fs system clock

fractional divider control for UART clock

0x02D8 FDC_DEBOUNCE_PCLK

fractional divider control for DEBOUNCE bus clock

0x02DC FDC_ADC_CLK

fractional divider control for control ADC system clock

0x02E0 FDC_DIO_PCLK

fractional divider control for DIO interface clock

0x02E4 FDC_AUDIO_PCLK

fractional divider control for audio bus clock

0x02E8 FDC_FRAMESYNCREF

fractional divider control for SRI frame sync reference

0x02EC FDC_CR_I2SIN_2_BCK

fractional divider control for I2SIN_2 bit clock

0x02F0 FDC_CR_I2SIN_1_BCK

fractional divider control for I2SIN_1 bit clock

0x2F4 FDC_CR_I2SOUT_BCK

fractional divider control for I2SOUT bit clock

0x02F8 FDC_I2S_WS

fractional divider control for I2S word select

0x02FC FDC_SDAC_NS_CLK

fractional divider control for SDAC new sample

0x300 FDC_AUDIO_SYSCLK

fractional divider control for audio system clock

0x0304 FDC_DCDC_CONVERTER_CLK fractional divider control for DC-to-DC converter clock

0x0308 FDC_CR_CLK_OUT1

fractional divider control for crystal output 1 from pad

0x030C FDC_CR_CLK_OUT2

fractional divider control for crystal output 2 from pad

0x0310 FDC_SRI_CHCLK

fractional divider control for SRI channel clock

0x0C00 CNF_POWERMODE

power-down CGU

0x0C04 CNF_WD_BARK

watchdog bark register

0x0C08 reserved

0xC0C reserved

0x0C10 OSC_ON

activate crystal oscillator

0x0C14 OSC_BYPASS

bypass crystal oscillator

0x0C18 CNF_UART_RST_N

reset for UART

0x0C1C CNF_I2SIN_1_RST_N

reset for I2S input 1

0x0C20 CNF_I2SIN_2_RST_N

reset for I2S input 2

0x0C24 CNF_I2SOUT_1_RST_N

reset for I2S output 1

0x0C28 CNF_I2SOUT_2_RST_N

reset for I2S output 2

0x0C2C CNF_DEC_RST_N

reset for decimation ï¬lter

0x0C30 CNF_INT_RST_N

reset for interpolation ï¬lter

0x0C34 CNF_SPDIF_RST_N

reset for SPDIF

0xC38 CNF_EPICS7B_RST_N

reset for EPICS7B

0x0C3C CNF_DIO2VPB0_RST_N

reset for VPB0 bridge

0x0C40 CNF_DIO2VPB1_RST_N

reset for UART VPB bridge

0x0C44 CNF_MS_I2C_RST_N

reset for M/S I2C-bus

SAA8200HL_2

Preliminary data sheet

Rev. 02 â 17 October 2005

20 of 71

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