SAA8200HL Datasheet, PDF (15/71 Pages) NXP Semiconductors – Ensation Base integrated wireless audio baseband

Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
Table 10: User register description …continued
Register name
Address
R/W Description
SRI_RX_ADDR
0x0 FFC8
W
serial radio interface DMA to
MEM start address
SRI_RX_BLKSIZE 0x0FFC7
W
serial radio interface DMA to
MEM block size
APLL_M
0x0 FFC6
W
direct control of audio PLL M
value
APLL_N
0x0 FFC5
W
direct control of audio PLL N
value
I2C_ADDR
0x0 FFC4
W
master/slave I²C-bus DMA
memory address
I2C_BLKSIZE
0x0 FFC3
W
master/slave I²C-bus DMA
block size
I2C_CONTROL
0x0 FFC2
W
master/slave I²C-bus control
MPI_DEVADDR
0x0 FFC1
W
MPI device address
Reset
0x000 0000
0x000 0000
0x000 0000
0x000 0000
0x002 8000
0x000 0000
0x000 0002
0x000 0048
7.2 VPB0 bridge
Section 7.2 specifies the interfaces and function of the VPB0 bridge. The VPB0 bridge
acts as a bridge between a range of RTG IP blocks using the VPB bus and the EPICS7B
DIO interface. Two bridges are used one to connect to several slow blocks and an
additional one specifically for the UART.
The VPB0 bridge forms the bridge between the EPICS7B and the clock generation unit,
SRI I²C-bus, watchdog timer, event router, I/O configuration and the audio configuration
respectively.
7.2.1 VPB0 bridge address definitions
Table 11: VPB0 bridge interface description
Base address Offset Key
0x 0000
0x0000 SCR_LP0
0x0004 SCR_HP0
0x0008 SCR_DCDC
0x000C SCR_SPDIF
0x0010 SCR_I2SIN_1
0x0014 SCR_I2SIN_2
0x0018 SCR_I2SOUT
0x001C SCR_SRI_GCHCLK
0x0020 SCR_CR_CLK_OUT1
0x0024 SCR_CR_CLK_OUT2
0x0028 SCR_SRI_CHCLK
0x002C FS1_ LP0
0x0030 FS1_ HP0
0x0034 FS1_ DCDC
0x0038 FS1_ SPDIF
Description
clock generation unit
switch control register for system PLL clock
switch control register for audio PLL clock
switch control register for DC-to-DC converter clock
switch control register for SPDIF clock
switch control register for I2SIN_1 bit clock
switch control register for I2SIN_2 bit clock
switch control register for I2SOUT bit clock
switch control register for SRI gated channel clock
switch control register for CR output 1 clock
switch control register for CR output 2 clock
switch control register for SRI reference channel clock
frequency select side 1 for system PLL clock
frequency select side 1 for audio PLL clock
frequency select side 1 for DC-to-DC converter clock
frequency select side 1 for SPDIF clock
SAA8200HL_2
Preliminary data sheet
Rev. 02 — 17 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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