SAA8200HL Datasheet, PDF (33/71 Pages) NXP Semiconductors – Ensation Base integrated wireless audio baseband

Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
Table 13: Mode settings
MODE[1:0]
00
01
10
11
Pin multiplexer mode
GPIO; high-impedance
normal operation; controlled by subsystem
GPIO drive LOW
GPIO drive HIGH
7.16 VPB1 bridge
This section describes the interfaces and function of the VPB1 bridge. The VPB1 bridge
acts as a bridge between the UART and the EPICS7B DIO interface. Two bridges are
used; one to connect to several slow blocks and an additional one specifically for the
universal synchronous receiver transmitter, which is commonly used to implement a serial
interface. In any case where a device needs a low overhead, standard, low performance
interface, a UART can be used. The UART includes advanced features like a fractional
clock divider.
Table 14: VPB1 bridge interface description
Base address Offset
Key
0x0000
0x0000
UART_RBR
0x0000
UART_THR
0x0004
UART_IER
0x0008
UART_IIR
0x0008
UART_FCR
0x000C
UART_LCR
0x0010
UART_MCR
0x0014
UART_LSR
0x0018
UART_MSR
0x001C
UART_SCR
0x0000
UART_DLL
0x0004
UART_DLM
0x0028
UART_FDR
Description
UART
receive FIFO
transmit FIFO
interrupt enable register
interrupt ID register
FIFO control register
line control register
modem control register
line status register
modem status register
scratch pad register
divisor latch LSB
divisor latch MSB
fractional divider register
7.17 UART configuration
The UART interface is used to be implemented as a serial interface to, for example a
modem and is compatible with the industry standards 16650 UARTs.
No full modem interface is included, only the CTS and RTS modem signals are available.
The UART interface can also be configured as an IrDA (InfraRed Digital Association) SIR
(Serial InfraRed) interface, which has a pulse and polarity compliancy with the IrDA
Version 1.0 Physical Layer Specification.
SAA8200HL_2
Preliminary data sheet
Rev. 02 — 17 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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