SAA8200HL Datasheet, PDF (16/71 Pages) NXP Semiconductors – Ensation Base integrated wireless audio baseband

Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
Table 11: VPB0 bridge interface description …continued
Base address Offset Key
0x003C FS1_ I2SIN_1
0x0040 FS1_ I2SIN_2
0x0044 FS1_ I2SOUT
0x0048 FS1_ SRI_GCHCLK
0x004C FS1_ CR_CLK_OUT1
0x0050 FS1_ CR_CLK_OUT2
0x0054 FS1_ SRI_CHCLK
0x0058 FS2_ LP0
0x005C FS2_ HP0
0x0060 FS2_ DCDC
0x0064 FS2_ SPDIF
0x0068 FS2_ I2SIN_1
0x006C FS2_ I2SIN_2
0x0070 FS2_ I2SOUT
0x0074 FS2_ SRI_GCHCLK
0x0078 FS2_ CR_CLK_OUT1
0x007C FS2_ CR_CLK_OUT2
0x0080 FS2_ SRI_CHCLK
0x0084 SSR_ LP0
0x0088 SSR_ HP0
0x008C SSR_ DCDC
0x0090 SSR_ SPDIF
0x0094 SSR_ I2SIN_1
0x0098 SSR_ I2SIN_2
0x009C SSR_ I2SOUT
0x00A0 SSR_ SRI_GCHCLK
0x00A4 SSR_ CR_CLK_OUT1
0x00A8 SSR_ CR_CLK_OUT2
0x00AC SSR_ SRI_CHCLK
0x00B0 PCR_SPD_SYSCLK
0x00B4 PCR_SYSCLK_DIV4
0x00B8 PCR_UART_UCLK
0x00BC PCR_VPB1_PCLK
0x00C0 PCR_UART_PCLK
0x00C4 PCR_DEBOUNCE_PCLK
0x00C8 PCR_CGU_PCLK
0x00CC PCR_WDOG_PCLK
0x00D0 PCR_ADC_PCLK
0x00D4 PCR_IOCONF_PCLK
0x00D8 PCR_EVENT_ROUTER_PCLK
0x00DC PCR_SRI_I2C_PCLK
Description
frequency select side 1 for I2SIN_1 bit clock
frequency select side 1 for I2SIN_2 bit clock
frequency select side 1 for I2SOUT bit clock
frequency select side 1 for SRI gated channel clock
frequency select side 1 for CR output 1 clock
frequency select side 1 for CR output 2 clock
frequency select side 1 for SRI reference channel clock
frequency select side 2 for system PLL clock
frequency select side 2 for audio PLL clock
frequency select side 2 for DC-to-DC converter clock
frequency select side 2 for SPDIF clock
frequency select side 2 for I2SIN_1 bit clock
frequency select side 2 for I2SIN_2 bit clock
frequency select side 2 for I2SOUT bit clock
frequency select side 2 for SRI gated channel clock
frequency select side 2 for CR output 1 clock
frequency select side 2 for CR output 2 clock
frequency select side 2 for SRI reference channel clock
frequency select status for system PLL clock
frequency select status for audio PLL clock
frequency select status for DC-to-DC converter clock
frequency select status for SPDIF clock
frequency select status for I2SIN_1 bit clock
frequency select status for I2SIN_2 bit clock
frequency select status for I2SOUT bit clock
frequency select status for SRI gated channel clock
frequency select status for CR output 1 clock
frequency select status for CR output 2 clock
frequency select status for SRI reference channel clock
power control register for system clock
power control register for 0.25 × f_s system clock
power control register for UART clock
power control register for VPB1 bus clock
power control register for UART bus clock
power control register for DEBOUNCE bus clock
power control register for CGU bus clock
power control register for WDOG bus clock
power control register for control ADC bus clock
power control register for IO configuration bus clock
power control register for event router bus clock
power control register for SRI I²C-bus clock
SAA8200HL_2
Preliminary data sheet
Rev. 02 — 17 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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