SAA8200HL Datasheet, PDF (23/71 Pages) NXP Semiconductors – Ensation Base integrated wireless audio baseband

Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
Table 11: VPB0 bridge interface description …continued
Base address Offset Key
0x0014 IOC_MODE0_SET
0x0018 IOC_MODE0_RESET
0x0020 IOC_MODE1
0x0024 IOC_MODE1_SET
0x0028 IOC_MODE1_RESET
0x 7000
0x0000 I2S_FORMAT_SETTINGS
0x0004 I2S_MUX_SETTINGS
0x0008 SPDIF_STATUS
0x000C SPDIF_IRQ_EN
0x0010 SPDIF_IRQ_STATUS
0x0014 SPDIF_IRQ_CLEAR
0x0018 SDAC_CTRL_INTI
0x001C SDAC_CTRL_INTO
0x0020 SDAC_SETTINGS
0x0024 SADC_CTRL_SDC
0x0028 SADC_CTRL_ADC
0x002C SADC_CTRL_DECI
0x0030 SADC_CTRL_DECO
0x0034 E7B_IRQ
0x0038 PD_ADC10B
0x003C SET_DCDC1V8_ADJUST
0x0040 SET_DCDC3V3_ADJUST
0x0044 DCDC_CLOCKSTABLE
Description
set mode 0
reset mode 0
load mode 1
set mode 1
reset mode 1
audio configuration
I²S-bus format settings
I²S-bus multiplexer settings
SPDIF status
SPDIF interrupt enable
SPDIF interrupt status
SPDIF interrupt clear
audio DAC input interpolation filter control
audio DAC output interpolation filter control
audio DAC control
audio ADC amplifiers control
audio ADC control
audio ADC input decimation filter control
audio ADC output decimation filter control
EPICS7B interrupt request
power-down control ADC
DC-to-DC converter adjust output voltage (1.8 V)
DC-to-DC converter adjust output voltage (3.3 V)
DC-to-DC converter clock stable signal
7.3 Clock generation unit
The Clock Generation Unit (CGU) generates all clock signals required for the
SAA8200HL, it contains:
• A crystal oscillator
• For low power mode the internal DC-to-DC converter clock can be used as system
clock
• An audio PLL to generate audio sample frequencies
• A system PLL to generate the clocks for the VPB bus and the DSP subsystem
• A clock switch block
• A configuration register block
• A reset and power block.
An 11.2896 MHz oscillator or an external 11.025 MHz clock (provided by the TEA7000)
can be used in combination with the two PLLs and the external clocks to generate the
system frequencies.
SAA8200HL_2
Preliminary data sheet
All PLLs are programmed with the registers in the register configuration block.
Rev. 02 — 17 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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