SAA8200HL Datasheet, PDF (19/71 Pages) NXP Semiconductors – Ensation Base integrated wireless audio baseband

Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
Table 11: VPB0 bridge interface description …continued
Base address Offset Key
Description
0x0228 ESR_UART_UCLK
enable fraction divider for UART clock
0x022C ESR_VPB1_PCLK
enable fraction divider for VPB1 bus clock
0x0230 ESR_UART_PCLK
enable fraction divider for UART bus clock
0x0234 ESR_DEBOUNCE_PCLK
enable fraction divider for DEBOUNCE bus clock
0x0238 ESR_CGU_PCLK
enable fraction divider for CGU bus clock
0x023C ESR_WDOG_PCLK
enable fraction divider for WDOG bus clock
0x0240 ESR_ADC_PCLK
enable fraction divider for control ADC bus clock
0x0244 ESR_IOCONF_PCLK
enable fraction divider for IO configuration bus clock
0x0248 ESR_EVENT_ROUTER_PCLK enable fraction divider for event router bus clock
0x024C ESR_SRI_I2C_PCLK
enable fraction divider for SRI I²C-bus clock
0x0250 ESR_ADC_CLK
enable fraction divider for control ADC system clock
0x0254 ESR_I2C_MS_PCLK
enable fraction divider for M/S I²C-bus clock
0x0258 ESR_RSC_PCLK
enable fraction divider for RSC bus clock
0x025C ESR_EXTDMACNTR_PCLK
enable fraction divider for external DMA controller clock
0x0260 ESR_DIO2VPB0 _PCLK
enable fraction divider for DIO2VPB0 bus clock
0x0264 ESR_DIO2VPB1_PCLK
enable fraction divider for DIO2VPB1 bus clock
0x0268 ESR_I2SIN_1 _PCLK
enable fraction divider for I2SIN_1 bus clock
0x026C ESR_I2SIN_2 _PCLK
enable fraction divider for I2SIN_2 bus clock
0x0270 ESR_I2SOUT_1 _PCLK
enable fraction divider for I2SOUT_1 bus clock
0x0274 ESR_I2SOUT_2_PCLK
enable fraction divider for I2SOUT_2 bus clock
0x0278 ESR_ADSS _PCLK
enable fraction divider for ADSS bus clock
0x027C ESR_AUDIO_CONFIG _PCLK enable fraction divider for audio configuration bus clock
0x0280 ESR_SPDIF _PCLK
enable fraction divider for SPDIF bus clock
0x0284 ESR_SRI _PCLK
enable fraction divider for SRI bus clock
0x0288 ESR_FRAMESYNCREF
enable fraction divider for SRI frame sync reference
0x028C ESR_CR_I2SIN_2_BCK
enable fraction divider for I2SIN_2 bit clock
0x0290 ESR_CR_I2SIN_1_BCK
enable fraction divider for I2SIN_1 bit clock
0x0294 ESR_CR_I2SOUT_BCK
enable fraction divider for I2SOUT bit clock
0x0298 ESR_CR_I2SIN_2_WS
enable fraction divider for I2SIN_2 word select
0x029C ESR_CR_I2SIN_1_WS
enable fraction divider for I2SIN_1 word select
0x02A0 ESR_CR_I2SOUT_WS
enable fraction divider for I2SOUT word select
0x02A4 ESR_SDAC_NS_CLK
enable fraction divider for SDAC new sample
0x02A8 ESR_SDAC_DSPCLK
enable fraction divider for SDAC DSP clock
0x02AC ESR_SADC_DECCLK
enable fraction divider for SADC decimation filter clock
0x02B0 ESR_SADC_SYSCLK
enable fraction divider for SADC system clock
0x02B4 ESR_DCDC_CONVERTER_CLK enable fraction divider for DC-to-DC converter clock
ESR_SPDIF_BCK
no fractional divider supported for this clock
ESR_I2SIN_1_BCK
no fractional divider supported for this clock
ESR_I2SIN_2_BCK
no fractional divider supported for this clock
ESR_I2SOUT_BCK
no fractional divider supported for this clock
ESR_SRI_GCC_SHO
no fractional divider supported for this clock
SAA8200HL_2
Preliminary data sheet
Rev. 02 — 17 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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