AMIS-30543 Datasheet, PDF (33/38 Pages) ON Semiconductor – Micro-Stepping Motor Driver

AMIS−30543
CS
DI
DATA from previous command or
NOT VALID after POR or RESET
DO
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
COMMAND
WRITE DATA to ADDR3
DATA
OLD DATA or NOT VALID
DATA
NEW DATA for ADDR3
DATA
OLD DATA from ADDR3
Figure 21. Single WRITE Operation Where DATA from the Master is Written in SPI Register with Address 3
Examples of combined READ and WRITE
Operations
In the following examples successive READ and WRITE
operations are combined. In Figure 22 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
by writing a control byte in Control Register at ADDR2.
Note that during the write command the old data of the
pointed register is returned at the moment the new data is
shifted in
Registers are updated with the internal
status at the rising edge of the internal
AMIS−30543 clock when CS = 1
CS
The NEW DATA is written into the
corresponding internal register at
the rising edge of CS
DI
DATA from previous
command or NOT VALID
after POR or RESET
DO
COMMAND
READ DATA
from ADDR4
DATA
OLD DATA
or NOT VALID
COMMAND
READ DATA
from ADDR5
DATA
DATA
from ADDR4
COMMAND
WRITE DATA
to ADDR 2
DATA
DATA
from ADDR5
DATA
NEW DATA
for ADDR2
DATA
OLD DATA
from ADDR2
Figure 22. 2 Successive READ Commands Followed by a WRITE Command
After the write operation the Master could initiate a read
back command in order to verify the data correctly written
as illustrated in Figure 23. During reception of the READ
command the old data is returned for a second time. Only
after receiving the READ command the new data is
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CS line is high, the first read out byte
might represent old status information.
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