AMIS-30543 Datasheet, PDF (30/38 Pages) ON Semiconductor – Micro-Stepping Motor Driver

AMIS−30543
The voltage regulator remains active but with reduced
current−output capability (I_LOADSLP). The watchdog timer
stops running and it’s value is kept in the counter. Upon
leaving sleep mode, this timer continues from the value it
had before entering sleep mode.
VBB
Normal operation is resumed after writing logic ‘0’ to bit
<SLP>. A startup time is needed for the charge pump to
stabilize. After this time, NXT commands can be issued.
VDD
tPU
V_DDH
POR/WD pin
t_POR
tDSPI
t
t
t_{WDRD tPOR}
Enable WD
> t_WDPR and < t_WDTO
Acknowledge WD
t
t_WDTO
= t_WDPR or = t_WDTO
WD timer
t
Figure 17. Watchdog Timing Diagram
NOTE: t_DSPI is the time needed by the external microcontroller to shift−in the <WDEN> bit after a powerup.
The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (See also Table 11: SPI
CONTROL REGISTERS. The timing is given in Table 10 below.
Table 10. WATCHDOG TIMEOUT INTERVAL AS FUNCTION OF WDT[3.0]
Index WDT[3:0]
0
0000
t_WDTO (ms)
32
Index WDT[3:0]
8
1000
1
0001
64
9
1001
2
0010
96
10
1010
3
0011
128
11
1011
4
0100
160
12
1100
5
0101
192
13
1101
6
0110
224
14
1110
7
0111
256
15
1111
t_WDTO (ms)
288
320
352
384
416
448
480
512
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