|
AMIS-30543 Datasheet, PDF (29/38 Pages) ON Semiconductor – Micro-Stepping Motor Driver | |||
|
◁ |
AMISâ30543
Error Output
This is a digital output to flag a problem to the external
microcontroller. The signal on this output is active low and
the logic combination of:
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR
<OVCYij> OR <OPENi> OR <CPFAIL>
Logic Supply Regulator
AMISâ30543 has an onâchip 5 V lowâdrop regulator
with external capacitor to supply the digital part of the chip,
some lowâvoltage analog blocks and external circuitry. The
voltage level is derived from an internal bandgap reference.
To calculate the available driveâcurrent for external
VBB
circuitry, the specified Iload should be reduced with the
consumption of internal circuitry (unloaded outputs) and the
loads connected to logic outputs. See Table 4. DC
parameters
PowerâOn Reset (POR) Function
The open drain output pin POR/WD provides an âactive
lowâ reset for external purposes. At powerup of
AMISâ30543, this pin will be kept low for some time to reset
for example an external microcontroller. A small analogue
filter avoids resetting due to spikes or noise on the VDD
supply.
VDD
tPU
t
tPD
VDDH
VDDL
t
< tRF
POR/WD pin
tPOR
tRF
Figure 16. PowerâonâReset Timing Diagram
Watchdog Function
The watchdog function is enabled/disabled through
<WDEN> bit (Table 11: SPI CONTROL REGISTERS).
Once this bit has been set to â1â (watchdog enable), the
microcontroller needs to reâwrite this bit to clear an internal
timer before the watchdog timeout interval expires. In case
the timer is activated and WDEN is acknowledged too early
(before tWDPR) or not within the interval (after tWDTO), then
a reset of the microcontroller will occur through POR/WD
pin. In addition, a warm/cold boot bit <WD> is available (see
Tables 14 and 15) for further processing when the external
microcontroller is alive again.
CLR pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside AMISâ30543, the input
CLR needs to be pulled to logic 1 during minimum time
given by tCLR (Table 5 AC Parameters). This reset function
clears all internal registers without the need of a
powerâcycle, except in sleep mode. Logic 0 on CLR pin
resumes normal operation again.
The voltage regulator and charge pump remains
functional during and after the reset and the POR/WD pin is
not activated. Watchdog function is reset completely.
Sleep Mode
The bit <SLP> in SPI Control Register 2 (See Table 10)
is provided to enter a soâcalled âsleep modeâ. This mode
allows reduction of currentâconsumption when the motor is
not in operation. The effect of sleep mode is as follows:
⢠The drivers are put in HiZ
⢠All analog circuits are disabled and in lowâpower mode
⢠All internal registers are maintaining their logic content
⢠NXT and DIR inputs are forbidden
⢠SPI communication remains possible (slight current
increase during SPI communication)
⢠Oscillator and digital clocks are silent, except during
SPI communication
⢠Registers cannot be cleared by using the CLR pin
VBB should be minimum 9 V to be able to enter
Sleep Mode.
http://onsemi.com
29
|
▷ |