PNX1502E Datasheet, PDF (98/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 2: Overview
Software decoded audio can be used for mixing with other audio for output along
one of the audio outputs. The sample rate is determined by the S/PDIF source,
and cannot be software controlled.
9. General Purpose Interfaces
VIP and QVCP share a set of pins with two general purpose interface modules, FGPI
and FGPO (respectively). The input and output data routers allocate a different
amount of pins between these four modules. The allocation depends on the operating
mode of each module. The following sections describe the different modes of the
input and output routers.
9.1 Video/Data Input Router
These inputs can provide combinations of the following functions:
• capture of video streams into DRAM, while performing horizontal scaling and
conversion to one of the standard pixel formats, simultaneously with data stream
capture
• low-latency reception of messages from another PNX15xx/952x Series
• capture of unstructured, infinite parallel data streams into DRAM
• capture of 1 or 2-dimensional parallel data streams in DRAM
• for message passing and data modes, operating speeds of up to 100 MHz, with
8-, 16- or 32-bit parallel data are supported, providing an aggregate input
bandwidth of up to 400 MB/s
The VDI pins consist of 38 pins, split into 32 data pins, 2 clock pins and 2 valid signals
that indicate whether data is valid on the respective clocks.
The operating modes of the video/data input router are set by the VDI_MODE MMIO
register. A subset of the operating modes are presented in Table 6, which combines
656 digital video source with streaming data inputs. A complete behavior of the
output router is available in Section 7. on page 3-124. Section 7.2 summarizes the
VIP features, while Section 9.3 presents some of the FGPI capabilities.
Table 6: Video/Data Input Operating Modes
mode
VIP function
FGPI function
VDI_MODE[1:0] = 0x0 (Default 8- or 10-bit ITU 656 with additional H&V
after reset)
synchronization signals
or
8- or 10-bit raw data
up to 22-bit data capture.
FGPI is usually set in 16- or 32-bit mode
storing into main memory respectively
16- or 32-bit words
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
2-98