PNX1502E Datasheet, PDF (654/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
Table 3: VLD Control
Name
Size
(Bits) Description
DMA_input_done_mode 1
When this bit is ‘0’, VLD sets the DMA_INPUT_DONE flag (in VLD_MC_STATUS
register) when the DMA_INP_CNT transitions from non-zero to zero.
When this bit is ‘1’, the same flag is set only with the additional condition that both DMA
input buffers are empty. The slice_start_code_strobe bit field must be set to ‘0’ in order to
update this field.
slice_start_code
8
Slice start code when the VLD is restarted; the slice_start_code_strobe bit field must be
set to ‘1’ in order to update this field.
slice_start_code_strobe 1
When CPU writes 1 into this field, VLD copies the value of slice_start_code into its
internal register. CPU should do this only when the VLD is stopped. This bit is always
read as 0.
3.2.4 VLD DMA Current Read Address (VLD_INP_ADR) and
Read Count (VLD_INP_CNT)
The CPU writes the main memory buffer address from which bitstream to be read by
VLD in VLD_INP_ADR register. The number of bytes to be read by the VLD is
updated by the CPU in the VLD_INP_CNT register.
The VLD unit uses two 64-byte buffers to store the input bitstream. The VLD reads
the bitstream data from the main memory and updates the VLD_INP_ADR and the
VLD_INP_CNT register. The content of the VLD_INP_ADR register reflects the next
or the current fetch address of the bitstream data.
The VLD interrupts the CPU when it has consumed all the given bitstream data in the
main memory (the DMA_INPUT_DONE condition). The value of the
DMA_INPUT_DONE_MODE bit in the VLD_CTL register is used to select the
condition for raising the DMA_INPUT_DONE flag. Refer to Table 3 for more details.
The VLD input address is word (32-bit) aligned and the count value in number of
bytes is also word aligned.
3.2.5 VLD DMA Macroblock Header Current Write Address (VLD_MBH_ADR)
The CPU writes the main memory macroblock header buffer address in the
VLD_MBH_ADR register in order to output the macroblock header data in main
memory. The VLD updates this address whenever data is transferred to main
memory via the DMA logic. The address always represents the next write address of
the macroblock header data. This register must be 32-bit aligned.
3.2.6 VLD DMA Macroblock Header Current Write Count
The CPU writes the main memory macroblock header buffer size formatted as the
number of 8-byte words into the VLD_MBH_CNT register in order to output the
macroblock header data in main memory. The VLD updates the buffer size whenever
data is transferred to main memory via the DMA logic. The buffer size always
represents the remaining empty buffer space.
Note that in MPEG-2 when Macroblock Headers are written to main memory, they are
written in groups of six 4-byte vectors (24 bytes).
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
21-654