PNX1502E Datasheet, PDF (553/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 17: SPDIF Output
• BUF_DONE - signals when the last word of a memory buffer is being requested
by the SPDO module. Note that this event is not dependent upon memory bus
latency.
The occurrence of this event represents a precise, periodic time interval which can be
used by system software for audio/video synchronization.
3.5 Endian Mode
The SPDIF descriptor is a 32-bit word memory data structure,
4. Signal Description
4.1 External Interface
Table 4: SPDIF Out External Signals
Signal Type Description
SPDO O
SPDIF output. Self clocking interface carrying either two-channel PCM data with samples up to 24 bits,
or encoded Dolby Digital (AC-3) or MPEG audio data for decoding by an external AC3 or MPEG
capable audio amplifier.
An external circuit as shown in Figure 3 is required to provide an electrically isolated
output and convert the 3.3 Volt output pin to a drive level of 0.5 V peak-peak into a 75
Ohm load, as required for consumer applications of IEC-60958.
PNX15xx/
SPDO
transformer
10 uF
240 ohm
1:1
RCA
1.5 - 7 MHz ^phono
110 ohm
Figure 3: Suggested External SPDIF Output Interface Circuitry
5. Register Descriptions
The base address for the PNX15xx/952x Series SPDIF Output Port module is 0x10
9000.
5.1 Register Summary
PNX15XX_PNX952X_SER_N_4
Product data sheet
Table 5: SPDIF Output Module Register Summary
Offset
Name
Description
0x10 9000
SPDO_STATUS
SPDIF Out Status
0x10 9004
SPDO_CTL
SPDIF Out general control register
0x10 9008
Reserved
0x10 900C
SPDO_BASE1
Base address of buffer1
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
17-553