PNX1502E Datasheet, PDF (247/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 7: PCI-XIO Module
Table 8: Registers Description
Bit Symbol
Acces
s
Value
Description
3
Prefetchable
R
cfg*
*Value is determined at boot time by pci_setup register.
2:0 Type
R
0
Indicates type 0 memory space (locatable anywhere in 32-bit
address space).
Offset 0x04 0058
Base Address 18 Image
31:4 Base Address 18
R/W*
1C00000
PCI configuration Base address for XIO.
This register affects the decode and routing of the bus controllers. It
should not be relied on as stable for 10 clocks after writing.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
3
Prefetchable
R
cfg*
*Value is determined at boot time by pci_setup register.
2:0 Type
R
0
Indicates PCI “type 0” memory space (locatable anywhere in 32-bit
address space).
Offset 0x04 006C
Subsystem ID/Subsystem Vendor ID Write Port
This register must be initialized before any PCI cycles will be entertained. The boot loader is expected to load the values at
boot time. This register is a Write-once/Read-only register (R/W1).
31:16 subsystem ID
R/W1 0
This is the write port for the Subsystem ID (PCI config 2C).
15:0 subsystem vendor ID R/W1 0
This is the write port for the Subsystem Vendor ID (PCI config 2C).
Offset 0x04 0074
Image of Configuration Reg 34
31:8 Reserved
R
0
7:0 CAP_PTR
R
40
Capabilities Pointer
Offset 0x04 007C
Image of Configuration Reg 3C
31:24 max_lat
R/W1 0x18
Max Latency
23:16 min_gnt
R/W1 0x09
Minimum Grant
15:8 interrupt pin
R
0x01
Interrupt pin information
7:0 Interrupt Line
R/W* 0x00
This register conveys interrupt line routing information.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
Offset 0x04 0080
Image of Configuration Reg 40
31:27 Reserved
R
00000
26 d2_support
R
cfg*
1 = Device supports D2 power management state.
*Value is determined by pci_setup register.
25 d1_support
R
cfg*
1 = Device supports D1 power management state.
*Value is determined by pci_setup register.
24:19 Reserved
R
0
18:16 version
R
010
Indicates compliance with version 1.1 of PM.
15:8 Next Item Pointer
R
00
There are no other extended capabilities.
7:0 Cap_ID
R
01
Indicates this is power management data structure.
Offset 0x04 0084
Image of Configuration Reg 44
31:1 Reserved
R
0
1:0 pwr_state
R/W* 0
Power State
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
7-247