PNX1502E Datasheet, PDF (737/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 23: LAN100 — Ethernet Media Access Controller
When a magic packet is detected, apart from the WakeupInt bit in the IntStatus
register, the MagicPacketWoL bit is set in the RxFilterWoLStatus register. Software
can reset the bit by writing a 1 to the corresponding bit of the RxFilterWoLClear
register.
Magic Packet WoL Example
An example of a Magic Packet with station address 11h 22h 33h 44h 55h 66h is as
follows. MISC indicates miscellaneous additional data bytes in the packet.
DESTINATION SOURCE MISC FF FF FF FF FF
FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44
55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33
44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22
33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11
22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 MISC CRC
5.14 Enabling and Disabling Receive and Transmit
5.14.1 Enabling and Disabling Reception
After reset, the receive function of the LAN100 is disabled. The receive function can
be enabled by the device driver by setting the RxEnable bit in the Command register
and the RECEIVE_ENABLE bit in the MAC1 configuration register of the LAN100.
The status of the Receive Datapath can be monitored by the device driver by reading
the RxStatus bit of the Status register. Figure 14 illustrates the finite state machine
(FSM) for generating the RxStatus bit.
ACTIVE
RxStatus=1
RxEnable
!RxEnable && not busy receiving
INACTIVE
RxStatus=0
Reset
Figure 14: Receive Active/Inactive state machine
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
23-737