PNX1502E Datasheet, PDF (533/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 16: Audio Input
Clocks are required to be running during HW/SW reset because synchronous reset is
used to initialize the logic. The unique feature with Audio is that unlike all other blocks
in the system, the Audio blocks default to the external clock source on any reset. If
the external clock does not exist when a HW reset is applied, then the logic is left
uninitialized without any indication.
3.3 Register Programming Guidelines
Software needs to ensure that the cap_enable bit (bit 30, AI_CTL) is programmed
after all the other registers have been programmed to ensure proper functionality.
Disabling and re-enabling capture
Here is a brief discussion on how the audio in block works if for some reason software
needs to disable the capture and consequently re-enable it. The Audio Input module
is continuously capturing and transferring data to memory through the adapter in the
system. The adapter threshold should be suitably set to satisfy the system latency
requirements. Once the adapter FIFO reaches the threshold, it will initiate a transfer
to memory. This behavior will continue until the capture is disabled. Once the capture
is disabled, the Audio In block will issue a FLUSH to the adapter so that it can flush its
FIFO and hence all the pertinent data that would reach memory. However, it must be
understood that disabling capture is not the same as applying software reset. Even
though capture is disabled, all the internal DMA state machines have pointers
pointing to addresses in memory corresponding to the transaction that was just
completed. So if the software intends to re-enable capture from scratch with new
pointers, there needs to be a software reset performed between disabling and re-
enabling the capture, along with optional reprogramming of the registers. Failure to
do a software reset will result in the Audio Input module behaving as though the
previous transaction is continuing with all the previous pointers active.
3.4 Serial Data Framing
The Audio In unit can accept data in a wide variety of serial data framing conventions.
Figure 3 illustrates the notion of a serial frame. If POLARITY = 1, CLOCK_EDGE = 0,
and EARLYMODE=0, a frame is defined with respect to the positive transition of the
WS signal as observed by a positive clock transition on SCK. (See Section 4..) Each
data bit sampled on positive SCK transitions has a specific bit position—i.e., once the
clock edge detects the WS transition, the next sample will be data bit position 0.
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
16-533